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    Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same
    12.
    发明授权
    Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same 失效
    具有鳍状有源区的非易失性存储器件及其制造方法

    公开(公告)号：US07605430B2

    公开(公告)日：2009-10-20

    申请号：US11474699

    申请日：2006-06-23

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC分类号： H01L29/76

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.

    摘要翻译： 非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。 翅片形有源区形成在器件隔离层的各部分之间。 侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。 因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。 侧壁保护层可以使用器件隔离层形成。 或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

    Nonvolatile Memory Devices Including a Resistor Region
    14.
    发明申请
    Nonvolatile Memory Devices Including a Resistor Region 审中-公开
    包括电阻器区域的非易失性存储器件

    公开(公告)号：US20080246073A1

    公开(公告)日：2008-10-09

    申请号：US12138712

    申请日：2008-06-13

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC分类号： H01L29/00

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

    摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

    摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 电池绝缘层形成在包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的半导体衬底的一部分上。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

    Methods of forming nonvolatile memory devices
    16.
    发明授权
    Methods of forming nonvolatile memory devices 有权
    形成非易失性存储器件的方法

    公开(公告)号：US07399672B2

    公开(公告)日：2008-07-15

    申请号：US11375983

    申请日：2006-03-15

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

    摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

    摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

    Nonvolatile memory devices and methods of forming the same
    18.
    发明申请
    Nonvolatile memory devices and methods of forming the same 有权
    非易失存储器件及其形成方法

    公开(公告)号：US20060208338A1

    公开(公告)日：2006-09-21

    申请号：US11375983

    申请日：2006-03-15

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Yoo-Cheol Shin ,  Jong-Sun Sel

    IPC分类号： H01L29/00

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568

    摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.

    摘要翻译： 形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。 在电阻器区域中的器件隔离层上形成第一导电层。 半导体衬底暴露在电池阵列区域中。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。 在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。 蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

    Non-volatile memory devices
    19.
    发明授权
    Non-volatile memory devices 有权
    非易失性存储器件

    公开(公告)号：US08675409B2

    公开(公告)日：2014-03-18

    申请号：US13463060

    申请日：2012-05-03

    申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

    发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Young-Woo Park ,  Jin-Taek Park

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/3427

    摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may cross the active region between the ground select line and the string select line with about a same first spacing provided between adjacent ones of the plurality of word lines and between a last of the plurality of memory cell word lines and the string select line. A second spacing may be provided between the ground select line and a first of the plurality of memory cell word lines.

    摘要翻译： 非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，与有源区交叉的接地选择线，以及与有源区交叉并与地选线相隔的串选择线。 多个存储单元字线可以与地线选择线和弦选择线之间的有源区域相交，并且与多个字线中的相邻字线之间以及多个存储单元字线中的最后一个之间提供大致相同的第一间隔 和字符串选择行。 可以在接地选择线和多个存储单元字线中的第一个之间提供第二间隔。

    SEMICONDUCTOR DEVICES IN WHICH A CELL GATE PATTERN AND A RESISTOR PATTERN ARE FORMED OF A SAME MATERIAL AND METHODS OF FORMING THE SAME
    20.
    发明申请
    SEMICONDUCTOR DEVICES IN WHICH A CELL GATE PATTERN AND A RESISTOR PATTERN ARE FORMED OF A SAME MATERIAL AND METHODS OF FORMING THE SAME 审中-公开
    细胞栅格图案和电阻图案的半导体器件形成相同的材料及其形成方法

    公开(公告)号：US20110031559A1

    公开(公告)日：2011-02-10

    申请号：US12905517

    申请日：2010-10-15

    申请人： Jong-Sun Sel ,  Jung-Dal Choi

    发明人： Jong-Sun Sel ,  Jung-Dal Choi

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L28/20

    摘要： A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, farming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.

    摘要翻译： 通过提供包括单元区域，外围电路区域和电阻器区域的半导体衬底形成半导体器件，在半导体衬底上形成器件隔离层以限定有源区，形成第一绝缘层和多晶硅 在外围电路区域的有源区上形成图案，在单元区域的有源区上形成第二绝缘层，电荷存储层和第三绝缘层，在半导体衬底上耕作导电层，并且使导电层 以在单元区域的第三绝缘层上形成导电图案，分别形成外围电路区域的有源区域的多晶硅图案和电阻器区域的半导体衬底。