公开(公告)号：US20080184064A1

公开(公告)日：2008-07-31

申请号：US11669667

申请日：2007-01-31

Applicant: Jui-Jen Wu ,  Yung-Lung Lin ,  Yen-Huei Chen ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Yung-Lung Lin ,  Yen-Huei Chen ,  Dao-Ping Wang

IPC: G06F11/16

CPC classification number: G11C29/808

Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.

Abstract translation: 本公开一般涉及用于存储器系统的高效冗余方案的方法和装置。 在一个实施例中，本公开涉及一种存储器电路，其具有：由多个存储单元限定的存储器阵列，所述多个存储器单元被布置成一列或多列和一行或多行，每个存储器单元与一对互补位线中的一个通信， 用字线; 多个IO电路，与所述多个存储单元列之一相关联的每个IO电路; 多个冗余位线，每个冗余位线与冗余位单元通信; 用于检测所述存储器电路中的有缺陷的存储单元的第一电路; 用于选择所述多个冗余位线中的一个用于从所述故障存储器单元切换到所述冗余存储器单元的第二电路; 以及用于将所述有缺陷的存储器单元的字线脉冲引导到所述选择的冗余存储单元的第三电路。

公开(公告)号：US20070159231A1

公开(公告)日：2007-07-12

申请号：US11328780

申请日：2006-01-10

Applicant: Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

Inventor： Yung-Lung Lin ,  Jui-Jen Wu ,  Hung-Jen Liao

IPC: H01H37/76

CPC classification number: G11C11/56 ,  G11C17/18

Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.

公开(公告)号：US20050194216A1

公开(公告)日：2005-09-08

申请号：US11062444

申请日：2005-02-22

Applicant: Yung-Lung Lin

Inventor： Yung-Lung Lin

IPC: F16N1/00

CPC classification number: G11B7/08582

Abstract: A self-lubricating device for supplying lubricant onto a threaded guide rod, includes a movable member disposed above the threaded guide rod, and has lower threads meshed with the threaded guide rod, and a lubricant supplier secured on the movable member, and has a nozzle extending into the movable member for supply of lubricant onto the threaded guide rod. The movable member is movable axially on the threaded guide rod in such a manner to rotate the latter upon actuated.

Abstract translation: 一种用于将润滑剂供给到螺纹导杆上的自润滑装置，包括设置在螺纹导杆上方的可动件，并具有与螺纹导向杆啮合的下部螺纹，以及固定在可动件上的润滑剂供应器，并具有喷嘴 延伸到可动构件中，以将润滑剂供应到螺纹导杆上。 可移动构件可以在螺纹导杆上以这样的方式轴向移动，以便在致动时使其旋转。

公开(公告)号：US08263173B2

公开(公告)日：2012-09-11

申请号：US11944415

申请日：2007-11-22

Applicant: Wei-Ya Wang ,  Shu-Chin Lee ,  Wen-Lung Chen ,  Fu-Chuan Tsai ,  Yung-Lung Lin ,  Yong-Mao Lin ,  Chun-Chieh Tsao

Inventor： Wei-Ya Wang ,  Shu-Chin Lee ,  Wen-Lung Chen ,  Fu-Chuan Tsai ,  Yung-Lung Lin ,  Yong-Mao Lin ,  Chun-Chieh Tsao

IPC: B05D5/06

CPC classification number: G03F7/0007 ,  G02B5/201 ,  G02B5/223

Abstract: A manufacturing method of a color filter including following steps is provided. First, a partition is formed on a substrate to form a plurality of pixel regions on the substrate. Next, a color pigment is provided along a continuous pigment-providing route, so as to form the color pigment on a sequence of pixel regions among the plurality of pixel regions and the partition. The method mentioned above can prevent the unfilled phenomenon of the pigment around the corners of the pixel region. Besides, a liquid crystal display panel having the color filter is also provided.

Abstract translation: 提供了包括以下步骤的滤色器的制造方法。 首先，在基板上形成分隔，以在基板上形成多个像素区域。 接着，沿着连续的颜料提供路径设置彩色颜料，以便在多个像素区域和分隔物之间的像素区域序列上形成彩色颜料。 上述方法可以防止像素区域的角部附近的颜料的未填充现象。 此外，还提供了具有滤色器的液晶显示面板。

公开(公告)号：US07468903B2

公开(公告)日：2008-12-23

申请号：US11598385

申请日：2006-11-13

Applicant: Dao-Ping Wang ,  Hung-Jen Liao ,  Kun Lung Chen ,  Yung-Lung Lin ,  Jui-Jen Wu ,  Chen Yen-Huei

Inventor： Dao-Ping Wang ,  Hung-Jen Liao ,  Kun Lung Chen ,  Yung-Lung Lin ,  Jui-Jen Wu ,  Chen Yen-Huei

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

公开(公告)号：US20080241429A1

公开(公告)日：2008-10-02

申请号：US11775877

申请日：2007-07-11

Applicant: Wen-Lung Chen ,  Shu-Chin Lee ,  Fu-Chuan Tsai ,  Wei-Ya Wang ,  Yong-Mao Lin ,  Chun-Chieh Tsao ,  Yung-Lung Lin ,  Yen-Heng Huang

Inventor： Wen-Lung Chen ,  Shu-Chin Lee ,  Fu-Chuan Tsai ,  Wei-Ya Wang ,  Yong-Mao Lin ,  Chun-Chieh Tsao ,  Yung-Lung Lin ,  Yen-Heng Huang

IPC: C09K19/02 ,  G03F1/00

CPC classification number: G02F1/133516 ,  G02F1/133512 ,  Y10T428/1036

Abstract: A color filter including a substrate, a bank and a plurality of color filter films is provided. The bank is disposed on the substrate and has many openings. The bank has both a bottom surface contacting the substrate and a top surface exceeding the bottom surface. An outline of the bottom surface does not exceed that of the top surface. Besides, the color filter films are disposed on the substrate exposed by the openings, respectively, and each of the color filter films has a curved top surface. In the above-mentioned color filter, wetability between the bank and the color filter films is favorable.

Abstract translation: 提供一种包括基板，堤和多个滤色膜的滤色器。 银行设置在基板上并具有许多开口。 银行具有与基板接触的底表面和超过底表面的顶表面。 底面的轮廓不超过顶面的轮廓。 此外，滤色膜分别设置在由开口露出的基板上，并且每个滤色膜具有弯曲的顶表面。 在上述滤色器中，堤和滤色膜之间的润湿性良好。

公开(公告)号：US20080137449A1

公开(公告)日：2008-06-12

申请号：US11636173

申请日：2006-12-08

Applicant: Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Kun-Lung Chen ,  Hung-Jen Liao ,  Yung-Lung Lin ,  Chen Yen-Huei ,  Dao-Ping Wang

IPC: G11C7/00

CPC classification number: G11C11/413

Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Abstract translation: 公开了一种写入动态功率控制电路，其包括BL及其互补BLB，耦合到BL和BLB的至少一个存储单元，具有耦合到BL的源极，漏极和栅极的第一NMOS晶体管， Vss和第一数据信号，分别具有耦合到BLB的源极，漏极和栅极的第二NMOS晶体管，Vss和第二数据信号，其中第二数据信号与第一数据信号互补， 第一PMOS晶体管，具有源极，漏极和栅极，分别耦合到高电压电源（CVDD）节点，BLB和BL，以及第二PMOS晶体管，其具有源极，漏极和栅极耦合到 CVDD节点，BL和BLB。

公开(公告)号：US20050134342A1

公开(公告)日：2005-06-23

申请号：US10741576

申请日：2003-12-18

Applicant: Yung-Lung Lin ,  Hung-Jen Liao

Inventor： Yung-Lung Lin ,  Hung-Jen Liao

IPC: H03K3/017 ,  H03K5/04 ,  H03K5/06

CPC classification number: H03K5/06

Abstract: A pulse generator is disclosed which comprises a clock buffer coupled to a data latch coupled to a delay unit; a logic device coupled to the delay unit and the data latch, the logic device adapted to logically combine signals generated from the delay unit and the data latch and to generate a signal pulse; and a signal reset unit coupled to the data latch. A method of generating a pulse is also disclosed, comprising generating a signal state by sensing a rising edge of an external clock; latching the signal state for generating a latched signal state; delaying the latched signal state for generating a delayed signal state; and logically combining the latched signal state and the delayed signal state for generating a signal pulse.

Abstract translation: 公开了一种脉冲发生器，其包括耦合到耦合到延迟单元的数据锁存器的时钟缓冲器; 耦合到所述延迟单元和所述数据锁存器的逻辑器件，所述逻辑器件适于逻辑地组合由所述延迟单元产生的信号和所述数据锁存器并产生信号脉冲; 以及耦合到数据锁存器的信号复位单元。 还公开了一种产生脉冲的方法，包括通过感测外部时钟的上升沿来产生信号状态; 锁存用于产生锁存信号状态的信号状态; 延迟锁存信号状态以产生延迟的信号状态; 并且逻辑地组合锁存信号状态和用于产生信号脉冲的延迟信号状态。

公开(公告)号：US07505319B2

公开(公告)日：2009-03-17

申请号：US11669667

申请日：2007-01-31

Applicant: Jui-Jen Wu ,  Yung-Lung Lin ,  Yen-Huei Chen ,  Dao-Ping Wang

Inventor： Jui-Jen Wu ,  Yung-Lung Lin ,  Yen-Huei Chen ,  Dao-Ping Wang

IPC: G11C11/34

CPC classification number: G11C29/808

Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.

Abstract translation: 本公开一般涉及用于存储器系统的高效冗余方案的方法和装置。 在一个实施例中，本公开涉及一种存储器电路，其具有：由多个存储单元限定的存储器阵列，所述多个存储器单元被布置成一列或多列和一行或多行，每个存储器单元与一对互补位线中的一个通信， 用字线; 多个IO电路，与所述多个存储单元列之一相关联的每个IO电路; 多个冗余位线，每个冗余位线与冗余位单元通信; 用于检测所述存储电路中的有缺陷的存储单元的第一电路; 用于选择所述多个冗余位线中的一个用于从所述故障存储器单元切换到所述冗余存储器单元的第二电路; 以及用于将所述有缺陷的存储器单元的字线脉冲引导到所述选择的冗余存储单元的第三电路。

公开(公告)号：US20080251884A1

公开(公告)日：2008-10-16

申请号：US11735454

申请日：2007-04-14

Applicant: Shine Chung ,  Yung-Lung Lin

Inventor： Shine Chung ,  Yung-Lung Lin

IPC: H01L29/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A fuse circuit comprising one or more one-time programmable electrical fuses; one or more unidirectional conductive devices each coupled to one of the fuses; a programming device coupled to the unidirectional conductive devices; and a selection module coupled to the electrical fuses for selecting a predetermined electrical fuse, wherein upon a selection by the selection module, a programming current is introduced through at least one selected electrical fuse, wherein the selection module is an N-to-one multiplexer selecting one of the N number of electrical fuses to be programmed, and the unidirectional conductive devices not coupled to the selected electrical fuse to prevent the programming current from interfering with the remaining electrical fuses.

Abstract translation: 一种包括一个或多个一次可编程电气保险丝的熔丝电路; 一个或多个单向导电装置，每个连接到所述保险丝之一; 耦合到所述单向导电装置的编程装置; 以及耦合到所述电熔丝的选择模块，用于选择预定的电熔丝，其中在所述选择模块进行选择时，通过至少一个所选择的电熔丝引入编程电流，其中所述选择模块是N对1多路复用器 选择要编程的N个电熔丝中的一个，以及未耦合到所选择的电熔丝的单向导电器件，以防止编程电流干扰剩余的电熔丝。