公开(公告)号：US20160085519A1

公开(公告)日：2016-03-24

申请号：US14863494

申请日：2015-09-24

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Lukas FUNKE

IPC: G06F9/44

CPC classification number: G06F8/35 ,  G06F17/5054

Abstract: A method for automatically determining models signals of an FPGA program which are readable from the FPGA with the aid of a readback following an FPGA build, including the following steps: generating an FPGA model and generating an FPGA code from the FPGA model, the method comprising the additional step of an automatic analysis for the purpose of identifying signals which are readable from the FPGA with the aid of a readback, prior to the completion of the step of generating the FPGA code from the FPGA model, and the method comprises the step of outputting signals which are readable from the FPGA with the aid of a readback. A data processing device is also provided for carrying out the method.

Abstract translation: 一种用于自动确定FPGA程序的模型信号的方法，其可以借助于FPGA构建之后的回读从FPGA中读取，包括以下步骤：从FPGA模型生成FPGA模型并生成FPGA代码，该方法包括 在从FPGA模型生成FPGA代码的步骤完成之前，借助于回读来鉴别可从FPGA读取的信号的自动分析的附加步骤包括以下步骤： 输出可从FPGA读取的信号，借助回读。 还提供了一种用于执行该方法的数据处理装置。

公开(公告)号：US20150379178A1

公开(公告)日：2015-12-31

申请号：US14753439

申请日：2015-06-29

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Lukas FUNKE

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F8/30

Abstract: A method for generating FPGA code based on an FPGA model with at least one signal value that is modeled as a constant. A constant is inserted with a predefined signal value in the FPGA model. A switching variable is set in the FPGA model for switching between a normal mode and a calibration mode for the FPGA code. The FPGA code is generated for the FPGA model having the implementation of the constants in the FPGA code, wherein the implementation of the constants when the switching variable is set for normal mode includes the implementation of the constants as a fixed value in the FPGA code, and the implementation of the constants when the switching variable is set for calibration mode includes the implementation of the constants as a modifiable signal value in the FPGA code. A method for calibrating an FPGA model is also provided.

Abstract translation: 一种基于具有至少一个被建模为常数的信号值的FPGA模型生成FPGA代码的方法。 在FPGA模型中使用预定义的信号值插入常数。 在FPGA模型中设置了切换变量，用于在正常模式和FPGA代码的校准模式之间切换。 为具有FPGA代码中常量实现的FPGA模型生成FPGA代码，其中当切换变量设置为正常模式时常数的实现包括将常数实现为FPGA代码中的固定值， 并且当切换变量设置为校准模式时，常数的实现包括在FPGA代码中将常数实现为可修改的信号值。 还提供了一种用于校准FPGA模型的方法。

公开(公告)号：US20150331983A1

公开(公告)日：2015-11-19

申请号：US14711116

申请日：2015-05-13

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Dominik LUBELEY

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build.

Abstract translation: 一种用于生成FPGA程序的网表的方法。 FPGA程序的模型由至少两个组件组成，每个组件在FPGA上分配一个单独的分区。 对于每个组件执行独立构建，并且从组件生成整体分类，其中构建作业在触发事件之后自动启动，并且触发事件是组件的保存，设计的组件的退出， 或时间控制，自动启动构建。

公开(公告)号：US20140229723A1

公开(公告)日：2014-08-14

申请号：US14177583

申请日：2014-02-11

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE

IPC: G06F9/44

CPC classification number: G06F9/4401 ,  G06F17/5027 ,  G06F17/5054

Abstract: A method for accessing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration into the FPGA, executing the FPGA hardware configuration in the FPGA, requesting a signal value of the FPGA, sending status data from a functional level of the FPGA to a configuration memory in its configuration level, reading the status data from the configuration memory as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model, using a hardware description language, including the steps of creating an FPGA hardware configuration, identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration, and creating a list with signal values accessible at runtime and the memory locations corresponding thereto.

Abstract translation: 一种在运行时访问FPGA的信号值的方法，包括将FPGA硬件配置加载到FPGA中的步骤，在FPGA中执行FPGA硬件配置，请求FPGA的信号值，从功能级别发送状态数据 的FPGA到其配置级的配置存储器，从配置存储器读取状态数据作为回读数据，并确定回读数据的信号值。 还提供了一种用于使用硬件描述语言来制作基于FPGA模型的FPGA构建的方法，所述方法包括以下步骤：创建FPGA硬件配置，识别用于基于至少一个基于信号值的状态数据的配置存储器的存储器位置 在FPGA硬件配置上，并创建一个列表，其中可以在运行时可访问的信号值和与之对应的存储单元。