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1.发明申请公开(公告)号：US20220060389A1
公开(公告)日：2022-02-24
申请号：US17518288
申请日：2021-11-03
发明人： Heiko KALTE , Dominik LUBELEY
摘要： A computer-implemented method for restructuring a predefined distributed real-time simulation network, wherein the simulation network has a plurality of network nodes and a plurality of data connections, wherein each network node has at least one data connection interface for connecting a data connection, wherein the network nodes are at least partially in communication via the data connections, and wherein during operation of the simulation network a simulation application is executed on at least one network node. The method permits a structure for the real-time simulation network to be automatically found in which the critical communication connections are reduced and avoided as much as possible by determining the topology of the simulation network so that topology information concerning the network nodes and the data connections between the network nodes is available by determining expected values for node data rates or node latencies for the network nodes of the simulation network.
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公开(公告)号：US20210256190A1
公开(公告)日：2021-08-19
申请号：US17178787
申请日：2021-02-18
发明人： Heiko KALTE , Dominik LUBELEY
IPC分类号： G06F30/392 , G06F30/337 , G06F30/347 , G06F30/343
摘要： A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.
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公开(公告)号：US20190213294A1
公开(公告)日：2019-07-11
申请号：US16207457
申请日：2018-12-03
发明人： Dominik LUBELEY , Heiko KALTE
IPC分类号： G06F17/50 , G06F16/901 , G06F16/903
摘要： A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.
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公开(公告)号：US20170329877A1
公开(公告)日：2017-11-16
申请号：US15585335
申请日：2017-05-03
发明人： Heiko KALTE , Dominik LUBELEY
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5027 , G06F17/5054
摘要： A method for creating an FPGA netlist generated from an FPGA source code and at least one shadow register. The FPGA source code defines at least one function and at least one signal. The shadow register is assigned to the at least one signal, and is arranged and provided to store the value of the assigned signal at runtime. An option for reading out the stored signal value at runtime is provided. The function defined in the FPGA source code is not changed by the shadow register. The function described by the FPGA source code is executed by the FPGA, and a functional decoupling of the shadow register from the function described in the FPGA source code is provided. Via the decoupling, the shadow register maintains the signal value stored at the time of the decoupling while the function described in the FPGA source code is being executed.
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公开(公告)号：US20150331983A1
公开(公告)日：2015-11-19
申请号：US14711116
申请日：2015-05-13
发明人： Heiko KALTE , Dominik LUBELEY
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build.
摘要翻译： 一种用于生成FPGA程序的网表的方法。 FPGA程序的模型由至少两个组件组成，每个组件在FPGA上分配一个单独的分区。 对于每个组件执行独立构建，并且从组件生成整体分类，其中构建作业在触发事件之后自动启动，并且触发事件是组件的保存，设计的组件的退出， 或时间控制，自动启动构建。
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公开(公告)号：US20210303501A1
公开(公告)日：2021-09-30
申请号：US17215967
申请日：2021-03-29
发明人： Andreas AGNE , Dominik LUBELEY , Heiko KALTE , Marc SCHLENGER
IPC分类号： G06F13/42
摘要： To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.
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公开(公告)号：US20190147129A1
公开(公告)日：2019-05-16
申请号：US16188893
申请日：2018-11-13
发明人： Heiko KALTE , Dominik LUBELEY
摘要： A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.
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公开(公告)号：US20170116363A1
公开(公告)日：2017-04-27
申请号：US15291113
申请日：2016-10-12
发明人： Dominik LUBELEY , Marc SCHLENGER , Heiko KALTE
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5022 , G06F17/5036 , G06F2217/78
摘要： A method for determining the power consumption of a programmable logic device, in which at least one configuration parameter is determined in accordance with a predefined configuration and at least one device parameter is determined in accordance with the programmable logic device. The predefined configuration is designed such that the programmable logic device exchanges data with a computing unit through at least one interface pin and receives data from at least one signal source and/or sends it to at least one signal receiver through at least one interface pin. At least one data characteristic of the data exchanged between the computing unit and the programmable logic device as well as at least one signal characteristic of the data received from the at least one signal source and/or sent to the at least one signal receiver are determined.
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