公开(公告)号：US20150347669A1

公开(公告)日：2015-12-03

申请号：US14823197

申请日：2015-08-11

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Lukas FUNKE

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027 ,  G06F17/5054

Abstract: A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values.

Abstract translation: 一种在运行时改变FPGA信号值的方法，包括将具有至少一个信号值的FPGA硬件配置加载到FPGA上的步骤，在FPGA上运行FPGA硬件配置，设置传输到FPGA的信号值 从信号值确定回写数据，将写回数据作为状态数据写入FPGA的配置存储器，并将状态数据从配置存储器传送到FPGA的功能级别。 还提供了一种用于执行FPGA构建的方法，包括以下步骤：创建具有多个信号值的FPGA硬件配置，在FPGA硬件配置的相邻区域中布置信号值，确定用于状态数据的配置存储器的存储器位置 基于FPGA硬件配置的多个信号值，并创建包含信号值的列表。

公开(公告)号：US20160085519A1

公开(公告)日：2016-03-24

申请号：US14863494

申请日：2015-09-24

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Lukas FUNKE

IPC: G06F9/44

CPC classification number: G06F8/35 ,  G06F17/5054

Abstract: A method for automatically determining models signals of an FPGA program which are readable from the FPGA with the aid of a readback following an FPGA build, including the following steps: generating an FPGA model and generating an FPGA code from the FPGA model, the method comprising the additional step of an automatic analysis for the purpose of identifying signals which are readable from the FPGA with the aid of a readback, prior to the completion of the step of generating the FPGA code from the FPGA model, and the method comprises the step of outputting signals which are readable from the FPGA with the aid of a readback. A data processing device is also provided for carrying out the method.

Abstract translation: 一种用于自动确定FPGA程序的模型信号的方法，其可以借助于FPGA构建之后的回读从FPGA中读取，包括以下步骤：从FPGA模型生成FPGA模型并生成FPGA代码，该方法包括 在从FPGA模型生成FPGA代码的步骤完成之前，借助于回读来鉴别可从FPGA读取的信号的自动分析的附加步骤包括以下步骤： 输出可从FPGA读取的信号，借助回读。 还提供了一种用于执行该方法的数据处理装置。

公开(公告)号：US20150379178A1

公开(公告)日：2015-12-31

申请号：US14753439

申请日：2015-06-29

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Lukas FUNKE

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F8/30

Abstract: A method for generating FPGA code based on an FPGA model with at least one signal value that is modeled as a constant. A constant is inserted with a predefined signal value in the FPGA model. A switching variable is set in the FPGA model for switching between a normal mode and a calibration mode for the FPGA code. The FPGA code is generated for the FPGA model having the implementation of the constants in the FPGA code, wherein the implementation of the constants when the switching variable is set for normal mode includes the implementation of the constants as a fixed value in the FPGA code, and the implementation of the constants when the switching variable is set for calibration mode includes the implementation of the constants as a modifiable signal value in the FPGA code. A method for calibrating an FPGA model is also provided.

Abstract translation: 一种基于具有至少一个被建模为常数的信号值的FPGA模型生成FPGA代码的方法。 在FPGA模型中使用预定义的信号值插入常数。 在FPGA模型中设置了切换变量，用于在正常模式和FPGA代码的校准模式之间切换。 为具有FPGA代码中常量实现的FPGA模型生成FPGA代码，其中当切换变量设置为正常模式时常数的实现包括将常数实现为FPGA代码中的固定值， 并且当切换变量设置为校准模式时，常数的实现包括在FPGA代码中将常数实现为可修改的信号值。 还提供了一种用于校准FPGA模型的方法。