公开(公告)号：US20150347669A1

公开(公告)日：2015-12-03

申请号：US14823197

申请日：2015-08-11

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Lukas FUNKE

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5027 ,  G06F17/5054

Abstract: A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values.

Abstract translation: 一种在运行时改变FPGA信号值的方法，包括将具有至少一个信号值的FPGA硬件配置加载到FPGA上的步骤，在FPGA上运行FPGA硬件配置，设置传输到FPGA的信号值 从信号值确定回写数据，将写回数据作为状态数据写入FPGA的配置存储器，并将状态数据从配置存储器传送到FPGA的功能级别。 还提供了一种用于执行FPGA构建的方法，包括以下步骤：创建具有多个信号值的FPGA硬件配置，在FPGA硬件配置的相邻区域中布置信号值，确定用于状态数据的配置存储器的存储器位置 基于FPGA硬件配置的多个信号值，并创建包含信号值的列表。

公开(公告)号：US20190165996A1

公开(公告)日：2019-05-30

申请号：US15822521

申请日：2017-11-27

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Matthias KLEMM ,  Heiko KALTE ,  Robert POLNAU ,  Thorsten BREHM ,  Jochen SAUER ,  Hans-Juergen MIKS ,  Robert LEINFELLNER ,  Ruediger KRAFT ,  Magnus ASPLUND ,  Matthias SCHMITZ

IPC: H04L12/24 ,  G06F9/54 ,  G06F13/42 ,  H04L29/08 ,  H04L12/18

Abstract: A method for operating a real-time-capable simulation network having multiple network nodes for computing a simulation model. The network nodes are connected to one another via a serial data bus, and the network nodes exchange data via data bus messages. At least one event-driven task of the simulation model is implemented on a first network node, and a nondeterministic triggering event is detected by a second network node. The second network node communicates the detected triggering event to the first network node and the first network node computes the event-driven task. A fast response time is achieved by the means that a detection signal is sent from the second network node in the form of a multicast data bus message or a broadcast data bus message to multiple network nodes of the simulation network or to all network nodes of the simulation network over the serial data bus.

公开(公告)号：US20220060389A1

公开(公告)日：2022-02-24

申请号：US17518288

申请日：2021-11-03

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Dominik LUBELEY

IPC: H04L12/24 ,  H04L12/26

Abstract: A computer-implemented method for restructuring a predefined distributed real-time simulation network, wherein the simulation network has a plurality of network nodes and a plurality of data connections, wherein each network node has at least one data connection interface for connecting a data connection, wherein the network nodes are at least partially in communication via the data connections, and wherein during operation of the simulation network a simulation application is executed on at least one network node. The method permits a structure for the real-time simulation network to be automatically found in which the critical communication connections are reduced and avoided as much as possible by determining the topology of the simulation network so that topology information concerning the network nodes and the data connections between the network nodes is available by determining expected values for node data rates or node latencies for the network nodes of the simulation network.

公开(公告)号：US20210303501A1

公开(公告)日：2021-09-30

申请号：US17215967

申请日：2021-03-29

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Andreas AGNE ,  Dominik LUBELEY ,  Heiko KALTE ,  Marc SCHLENGER

IPC: G06F13/42

Abstract: To program a first programmable gate array, for example a first FPGA, in a distributed computer system, a configuration of a first configuration logic on the first programmable gate array is provided. The first configuration logic is configured to receive a first user bitstream from a configuration software for configuring a first user logic on the first programmable gate array and to store the first user bitstream on a non-volatile memory of the first programmable gate array for the purpose of subsequently configuring a first user logic on the first programmable gate array according to the specifications from the first user bitstream. In an expansion stage of the invention, a configuration of a programming logic on the first programmable gate array is also provided for programming a second programmable gate array, which is connected to the first programmable gate array to form a daisy chain.

公开(公告)号：US20190147129A1

公开(公告)日：2019-05-16

申请号：US16188893

申请日：2018-11-13

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Dominik LUBELEY

IPC: G06F17/50 ,  G06F11/36 ,  G06F9/30

Abstract: A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.

公开(公告)号：US20170116363A1

公开(公告)日：2017-04-27

申请号：US15291113

申请日：2016-10-12

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Dominik LUBELEY ,  Marc SCHLENGER ,  Heiko KALTE

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5022 ,  G06F17/5036 ,  G06F2217/78

Abstract: A method for determining the power consumption of a programmable logic device, in which at least one configuration parameter is determined in accordance with a predefined configuration and at least one device parameter is determined in accordance with the programmable logic device. The predefined configuration is designed such that the programmable logic device exchanges data with a computing unit through at least one interface pin and receives data from at least one signal source and/or sends it to at least one signal receiver through at least one interface pin. At least one data characteristic of the data exchanged between the computing unit and the programmable logic device as well as at least one signal characteristic of the data received from the at least one signal source and/or sent to the at least one signal receiver are determined.

公开(公告)号：US20210256190A1

公开(公告)日：2021-08-19

申请号：US17178787

申请日：2021-02-18

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Dominik LUBELEY

IPC: G06F30/392 ,  G06F30/337 ,  G06F30/347 ,  G06F30/343

Abstract: A method for planning the design of partitions for a programmable gate array comprising different types of logic blocks of predetermined position, and a plurality of program routines comprising at least one first program routine and at least one further program routine. A mapping of a first partition of the programmable gate array with the first program routine and at least one further partition of the programmable gate array with the at least one further program routine is performed. The need of the first program routine for the individual types of logic blocks is determined. Meeting this need with the logic block resources of corresponding type available in the first partition. At least one logic block of corresponding type from the further partition or at least one of the further partitions into the first partition is transferred.

公开(公告)号：US20190213294A1

公开(公告)日：2019-07-11

申请号：US16207457

申请日：2018-12-03

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Dominik LUBELEY ,  Heiko KALTE

IPC: G06F17/50 ,  G06F16/901 ,  G06F16/903

Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.

公开(公告)号：US20170329877A1

公开(公告)日：2017-11-16

申请号：US15585335

申请日：2017-05-03

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE ,  Dominik LUBELEY

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5027 ,  G06F17/5054

Abstract: A method for creating an FPGA netlist generated from an FPGA source code and at least one shadow register. The FPGA source code defines at least one function and at least one signal. The shadow register is assigned to the at least one signal, and is arranged and provided to store the value of the assigned signal at runtime. An option for reading out the stored signal value at runtime is provided. The function defined in the FPGA source code is not changed by the shadow register. The function described by the FPGA source code is executed by the FPGA, and a functional decoupling of the shadow register from the function described in the FPGA source code is provided. Via the decoupling, the shadow register maintains the signal value stored at the time of the decoupling while the function described in the FPGA source code is being executed.

公开(公告)号：US20160162298A1

公开(公告)日：2016-06-09

申请号：US14962359

申请日：2015-12-08

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko KALTE

IPC: G06F9/44

CPC classification number: G06F9/4401 ,  G06F17/5027 ,  G06F17/5054

Abstract: A method for accessing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration into the FPGA, executing the FPGA hardware configuration in the FPGA, requesting a signal value of the FPGA, sending status data from a functional level of the FPGA to a configuration memory in its configuration level, reading the status data from the configuration memory as readback data, and determining the signal value of the readback data. A method is also provided for making an FPGA build, based on an FPGA model, using a hardware description language, including the steps of creating an FPGA hardware configuration, identifying memory locations of a configuration memory for status data of at least one signal value based on the FPGA hardware configuration, and creating a list with signal values accessible at runtime and the memory locations corresponding thereto.

Abstract translation: 一种在运行时访问FPGA的信号值的方法，包括将FPGA硬件配置加载到FPGA中的步骤，在FPGA中执行FPGA硬件配置，请求FPGA的信号值，从功能级别发送状态数据 的FPGA到其配置级的配置存储器，从配置存储器读取状态数据作为回读数据，并确定回读数据的信号值。 还提供了一种用于使用硬件描述语言来制作基于FPGA模型的FPGA构建的方法，所述方法包括以下步骤：创建FPGA硬件配置，识别用于基于至少一个基于信号值的状态数据的配置存储器的存储器位置 在FPGA硬件配置上，并创建一个列表，其中可以在运行时可访问的信号值和与之对应的存储单元。