公开(公告)号：US20060186918A1

公开(公告)日：2006-08-24

申请号：US11065019

申请日：2005-02-23

申请人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri

发明人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Chandra Mulpuri

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US06980025B1

公开(公告)日：2005-12-27

申请号：US10654517

申请日：2003-09-02

申请人： Hare Krishna Verma ,  Ashok Vittal

发明人： Hare Krishna Verma ,  Ashok Vittal

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1733

摘要： A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.

摘要翻译： 描述了可以被配置为组合逻辑，顺序逻辑或路由单元的函数发生器。 功能发生器耦合到从多个输入中选择导线的多个选择器块。 选定的导线是函数发生器的输入。 当配置为组合逻辑单元时，函数发生器可以生成其输入的任何函数。 函数发生器配置为顺序逻辑单元时，作为一个寄存器，其中任何一个输入都可以被指向输入数据，清零，时钟使能或复位信号。 寄存器可配置为下降沿或上升沿触发器或正或负电平敏感锁存器。 作为路由元件，逻辑单元选择其输入之一。 可编程单元的输出可以扇出到另一个集成单元的一个或多个输入端。

公开(公告)号：US20050206406A1

公开(公告)日：2005-09-22

申请号：US11128575

申请日：2005-05-14

申请人： Hare Verma ,  Ashok Vittal

发明人： Hare Verma ,  Ashok Vittal

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1733

摘要： A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.

摘要翻译： 描述了可以被配置为组合逻辑，顺序逻辑或路由单元的函数发生器。 功能发生器耦合到从多个输入中选择导线的多个选择器块。 选定的导线是函数发生器的输入。 当配置为组合逻辑单元时，函数发生器可以生成其输入的任何函数。 函数发生器配置为顺序逻辑单元时，作为一个寄存器，其中任何一个输入都可以被指向输入数据，清零，时钟使能或复位信号。 寄存器可配置为下降沿或上升沿触发器或正或负电平敏感锁存器。 作为路由元件，逻辑单元选择其输入之一。 可编程单元的输出可以扇出到另一个集成单元的一个或多个输入。