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    PROGRAMMABLE LOGIC ACCELERATOR IN SYSTEM ON CHIP
    1.
    发明申请
    PROGRAMMABLE LOGIC ACCELERATOR IN SYSTEM ON CHIP 审中-公开

    公开(公告)号：US20180012637A1

    公开(公告)日：2018-01-11

    申请号：US15713281

    申请日：2017-09-22

    申请人： Hare Krishna VERMA

    发明人： Hare Krishna VERMA

    IPC分类号： G11C7/10 ,  G11C5/06

    CPC分类号： G11C7/10 ,  G11C5/06 ,  H03K19/17756 ,  H03K19/17776

    摘要： A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.

    Programmable Logic Accelerator in System on Chip
    3.
    发明申请
    Programmable Logic Accelerator in System on Chip 审中-公开

    公开(公告)号：US20170206939A1

    公开(公告)日：2017-07-20

    申请号：US14997595

    申请日：2016-01-18

    申请人： Hare Krishna Verma

    发明人： Hare Krishna Verma

    IPC分类号： G11C7/10 ,  G11C5/06

    CPC分类号： G11C7/10 ,  G11C5/06 ,  H03K19/17756 ,  H03K19/17776

    摘要： A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.

    Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes
    4.
    发明授权
    Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes 有权
    可编程逻辑中使用串行链接和新型选择方案的多功能多路复用器结构

    公开(公告)号：US07358761B1

    公开(公告)日：2008-04-15

    申请号：US11040633

    申请日：2005-01-21

    申请人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

    发明人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1737

    摘要： Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.

    摘要翻译： 逻辑设计装置和方法提供可编程逻辑结构中的串行复用器链，链中的每个元件选择块的输出，或者从链的早期元素传递输出。 选择行是可配置函数发生器的解码器结构或输出，在上电时配置，以创建正确的选择。 使用这种结构，可以创建更大的多路复用器，包括优先复用器，三态总线或更大的查找表（LUT）。 这些新颖的结构可以实现优先级，非优先级或三态多路复用器。

    Programmable logic accelerator in system on chip
    5.
    发明授权
    Programmable logic accelerator in system on chip 有权

    公开(公告)号：US10210914B2

    公开(公告)日：2019-02-19

    申请号：US15713281

    申请日：2017-09-22

    申请人： Hare Krishna Verma

    发明人： Hare Krishna Verma

    IPC分类号： G11C7/10 ,  G11C5/06 ,  H03K19/177

    摘要： A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.

    System and method of signal processing engines with programmable logic fabric
    7.
    发明授权
    System and method of signal processing engines with programmable logic fabric 有权
    具有可编程逻辑结构的信号处理引擎的系统和方法

    公开(公告)号：US08131909B1

    公开(公告)日：2012-03-06

    申请号：US11857858

    申请日：2007-09-19

    申请人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

    发明人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

    IPC分类号： G06F13/00 ,  G06F7/38

    CPC分类号： G06F7/483 ,  G06F7/5443

    摘要： A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

    摘要翻译： 使用耦合到可编程逻辑结构的一个或多个信号处理引擎来描述高性能现场可编程门阵列。 每个信号处理引擎包括用于执行指定任务的信号处理单元和用于将基于总线的输入路由到基于总线的输出的基于总线的可配置连接盒。 信号处理单元具有用于计算的浮点单元（FPU）/乘法累加（MAC）和用于存储信息的寄存器文件。 可编程逻辑结构耦合到一个或多个信号处理引擎，用于在信号处理引擎之间路由信息。

    System and method of configurable bus-based dedicated connection circuits
    8.
    发明授权
    System and method of configurable bus-based dedicated connection circuits 有权
    基于可配置总线的专用连接电路的系统和方法

    公开(公告)号：US07970979B1

    公开(公告)日：2011-06-28

    申请号：US11857661

    申请日：2007-09-19

    申请人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

    发明人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

    IPC分类号： G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F7/38 ,  H03K19/173 ,  H03K19/177

    CPC分类号： G06F7/483 ,  G06F7/5443 ,  H03K19/17736

    摘要： A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

    摘要翻译： 使用耦合到可编程逻辑结构的一个或多个信号处理引擎来描述高性能现场可编程门阵列。 每个信号处理引擎包括用于执行指定任务的信号处理单元和用于将基于总线的输入路由到基于总线的输出的基于总线的可配置连接盒。 信号处理单元具有用于计算的浮点单元（FPU）/乘法累加（MAC）和用于存储信息的寄存器文件。 可编程逻辑结构耦合到一个或多个信号处理引擎，用于在信号处理引擎之间路由信息。

    Programmable function generator and method operating as combinational, sequential, and routing cells
    9.
    发明授权
    Programmable function generator and method operating as combinational, sequential, and routing cells 失效
    可编程函数发生器和方法作为组合，顺序和路由单元操作

    公开(公告)号：US06980025B1

    公开(公告)日：2005-12-27

    申请号：US10654517

    申请日：2003-09-02

    申请人： Hare Krishna Verma ,  Ashok Vittal

    发明人： Hare Krishna Verma ,  Ashok Vittal

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1733

    摘要： A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.

    摘要翻译： 描述了可以被配置为组合逻辑，顺序逻辑或路由单元的函数发生器。 功能发生器耦合到从多个输入中选择导线的多个选择器块。 选定的导线是函数发生器的输入。 当配置为组合逻辑单元时，函数发生器可以生成其输入的任何函数。 函数发生器配置为顺序逻辑单元时，作为一个寄存器，其中任何一个输入都可以被指向输入数据，清零，时钟使能或复位信号。 寄存器可配置为下降沿或上升沿触发器或正或负电平敏感锁存器。 作为路由元件，逻辑单元选择其输入之一。 可编程单元的输出可以扇出到另一个集成单元的一个或多个输入端。

    Programmable logic accelerator in system on chip
    10.
    发明授权
    Programmable logic accelerator in system on chip 有权

    公开(公告)号：US09812180B2

    公开(公告)日：2017-11-07

    申请号：US14997595

    申请日：2016-01-18

    申请人： Hare Krishna Verma

    发明人： Hare Krishna Verma

    IPC分类号： G11C7/10 ,  G11C5/06

    CPC分类号： G11C7/10 ,  G11C5/06 ,  H03K19/17756 ,  H03K19/17776

    摘要： A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.