公开(公告)号：US08699985B1

公开(公告)日：2014-04-15

申请号：US12770622

申请日：2010-04-29

Applicant: Wing J. Mar

Inventor： Wing J. Mar

IPC: H04B1/26 ,  H04B15/00

CPC classification number: G06F1/0328 ,  G06F2211/902

Abstract: A signal processor includes a frequency generator that employs a direct digital synthesizer (DDS) to generate a first local oscillator (LO) signal with a variable first LO frequency. The signal processor also includes an oscillator generating a second LO signal having a second LO frequency. The DDS employs programmable frequency control word and a sampling clock signal having a variable sampling clock frequency that is derived from the second LO frequency, to generate a DDS output signal from which the first LO signal is produced. The variable sampling clock frequency and the programmable frequency control word are selected to avoid crossing spurs in the frequency spectrum of the DDS output signal.

Abstract translation: 信号处理器包括使用直接数字合成器（DDS）产生具有可变的第一LO频率的第一本地振荡器（LO）信号的频率发生器。 信号处理器还包括产生具有第二LO频率的第二LO信号的振荡器。 DDS采用可编程频率控制字和具有从第二LO频率导出的可变采样时钟频率的采样时钟信号，以产生产生第一LO信号的DDS输出信号。 选择可变采样时钟频率和可编程频率控制字，以避免在DDS输出信号的频谱中交叉杂波。

公开(公告)号：US08583714B2

公开(公告)日：2013-11-12

申请号：US12704828

申请日：2010-02-12

Applicant: Steven E. Turner

Inventor： Steven E. Turner

IPC: G06F1/02

CPC classification number: G06F1/0328

Abstract: A DDS system is disclosed that is configured to provide a variable clock delay that allows timing of data coming out of the ROM to be adjusted. In one example case, a DDS system is provided that includes a ROM for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values, and delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system. The delay circuitry may include, for instance, delay elements that can be selected alone or in combination to adjust the timing. The timing can be adjusted, for example, by adjusting delay of a clock signal that clocks one or more ROM pipeline registers. The system may include a phase accumulator and DAC, and adjusting the timing may include adjusting delay of a clock signal that clocks one or more DAC pipeline registers.

Abstract translation: 公开了一种DDS系统，其被配置为提供允许调整从ROM出来的数据定时的可变时钟延迟。 在一个示例情况下，提供了一种DDS系统，其包括用于存储相位到幅度转换数据的ROM并且产生对应于各个数字相位值的数字幅度值的延迟电路，以及用于调整由ROM输出的数据的定时以补偿 DDS系统的传播延迟。 延迟电路可以包括例如可以单独或组合地选择以调整定时的延迟元件。 可以例如通过调整对一个或多个ROM流水线寄存器进行定时的时钟信号的延迟来调整定时。 该系统可以包括相位累加器和DAC，并且调整定时可以包括调整对一个或多个DAC流水线寄存器进行计时的时钟信号的延迟。

公开(公告)号：US20110199128A1

公开(公告)日：2011-08-18

申请号：US12704828

申请日：2010-02-12

Applicant: Steven E. Turner

Inventor： Steven E. Turner

IPC: H03B21/00

CPC classification number: G06F1/0328

Abstract: A DDS system is disclosed that is configured to provide a variable clock delay that allows timing of data coming out of the ROM to be adjusted. In one example case, a DDS system is provided that includes a ROM for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values, and delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system. The delay circuitry may include, for instance, delay elements that can be selected alone or in combination to adjust the timing. The timing can be adjusted, for example, by adjusting delay of a clock signal that clocks one or more ROM pipeline registers. The system may include a phase accumulator and DAC, and adjusting the timing may include adjusting delay of a clock signal that clocks one or more DAC pipeline registers.

Abstract translation: 公开了一种DDS系统，其被配置为提供允许调整从ROM出来的数据定时的可变时钟延迟。 在一个示例情况下，提供了一种DDS系统，其包括用于存储相位到幅度转换数据的ROM并且产生对应于各个数字相位值的数字幅度值的延迟电路，以及用于调整由ROM输出的数据的定时以补偿 DDS系统的传播延迟。 延迟电路可以包括例如可以单独或组合地选择以调整定时的延迟元件。 可以例如通过调整对一个或多个ROM流水线寄存器进行定时的时钟信号的延迟来调整定时。 该系统可以包括相位累加器和DAC，并且调整定时可以包括调整对一个或多个DAC流水线寄存器进行计时的时钟信号的延迟。

公开(公告)号：US07933942B2

公开(公告)日：2011-04-26

申请号：US11540810

申请日：2006-09-29

Applicant: William Scott McDonald

Inventor： William Scott McDonald

IPC: G06F1/02

CPC classification number: G06F1/0328 ,  G06F1/022

Abstract: An automatic test system that includes low cost and accurate circuitry for generating sinusoidal signals. Each sinusoidal signal generator produces a series of digital values approximating a sine wave. These values are computed, avoiding the need for large memories to store tables representing sine waves. Inaccuracies in the representation of the sine waves do not impact the accuracy of the resultant sine wave because circuitry used to correct for non-linearity errors in a digital-to-analog converter is programmed to also correct for errors introduced by approximating a sine wave with a computed function. A simple parabolic function may be used to compute approximations of a sine wave.

Abstract translation: 一种自动测试系统，包括用于产生正弦信号的低成本和精确电路。 每个正弦信号发生器产生近似正弦波的一系列数字值。 计算这些值，避免需要大的存储器来存储表示正弦波的表。 由于用于校正数模转换器中的非线性误差的电路被编程为对通过近似正弦波引入的误差进行校正，所以正弦波的表示中的不准确性不会影响所得正弦波的精度， 一个计算函数。 可以使用简单的抛物线函数来计算正弦波的近似。

公开(公告)号：US07907028B1

公开(公告)日：2011-03-15

申请号：US12366582

申请日：2009-02-05

Applicant: Robert Mack ,  Timothy Chen

Inventor： Robert Mack ,  Timothy Chen

IPC: H03B28/00 ,  H03K5/01 ,  H03L1/00

CPC classification number: G06F1/022 ,  G06F1/0328 ,  G06F1/08 ,  H03B28/00 ,  H03B2200/0088 ,  H03L1/00 ,  H03L7/0994

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract translation: 一种用于通过改变用于增加NCO中的累加器的步长值来补偿NCO抖动以补偿不准确或不稳定的方法。 在一种方法中，可以监视累加器中的余数，并且可以产生接近理想时钟的当前边缘的补偿时钟。 在另一种方法中，在理想时钟的当前边缘被错过之后，可以产生靠近理想时钟的下一个边缘的补偿时钟。 步数值可以存储在可以是寄存器的存储器中。 抖动补偿器可以包括用于监视累加器中的余数的比较器或用于检测是否错过理想时钟的检测器。 抖动补偿器还可以将步长值改变为更快时钟的步进值以补偿抖动。

公开(公告)号：US07834713B2

公开(公告)日：2010-11-16

申请号：US12039873

申请日：2008-02-29

Applicant: Stephen D. Larkin ,  Jeffrey H. Blake ,  Joseph F. Xavier ,  David E. Majchrzak

Inventor： Stephen D. Larkin ,  Jeffrey H. Blake ,  Joseph F. Xavier ,  David E. Majchrzak

IPC: H03B21/00

CPC classification number: G06F1/0328

Abstract: A method for controlling a synthesized local oscillator (SLO) includes: receiving a control input specifying a desired SLO output; receiving reference clock signal; generating a predefined set of dynamic clock signals from the reference clock signal; selecting a dynamic clock signal from the predefined set of dynamic clock signals in response to the control input; using the dynamic clock signal as an input to a direct digital synthesizer (DDS) module to generate a DDS output signal; selecting a DDS output band in response to the control input, the DDS output band including one of a baseband and an alias band; and processing the DDS output band to generate the SLO output.

Abstract translation: 一种用于控制合成本地振荡器（SLO）的方法包括：接收指定期望的SLO输出的控制输入; 接收参考时钟信号; 从所述参考时钟信号产生预定义的一组动态时钟信号; 响应于所述控制输入，从所述预定义的一组动态时钟信号中选择动态时钟信号; 使用动态时钟信号作为直接数字合成器（DDS）模块的输入，以产生DDS输出信号; 响应于控制输入选择DDS输出频带，DDS输出频带包括基带和别名频带之一; 并处理DDS输出频带以产生SLO输出。

公开(公告)号：US20080109504A1

公开(公告)日：2008-05-08

申请号：US11540810

申请日：2006-09-29

Applicant: William Scott McDonald

Inventor： William Scott McDonald

IPC: G06F1/02

CPC classification number: G06F1/0328 ,  G06F1/022

Abstract: An automatic test system that includes low cost and accurate circuitry for generating sinusoidal signals. Each sinusoidal signal generator produces a series of digital values approximating a sine wave. These values are computed, avoiding the need for large memories to store tables representing sine waves. Inaccuracies in the representation of the sine waves do not impact the accuracy of the resultant sine wave because circuitry used to correct for non-linearity errors in a digital-to-analog converter is programmed to also correct for errors introduced by approximating a sine wave with a computed function. A simple parabolic function may be used to compute approximations of a sine wave.

Abstract translation: 一种自动测试系统，包括用于产生正弦信号的低成本和精确电路。 每个正弦信号发生器产生近似正弦波的一系列数字值。 计算这些值，避免需要大的存储器来存储表示正弦波的表。 由于用于校正数模转换器中的非线性误差的电路被编程为对通过近似正弦波引入的误差进行校正，所以正弦波的表示中的不准确性不会影响所得正弦波的精度， 一个计算函数。 可以使用简单的抛物线函数来计算正弦波的近似。

公开(公告)号：US07365608B2

公开(公告)日：2008-04-29

申请号：US11297003

申请日：2005-12-08

Applicant: Hans Juergen Tucholski

Inventor： Hans Juergen Tucholski

IPC: H03B23/00

CPC classification number: G06F1/08 ,  G06F1/0328 ,  H03L7/16

Abstract: A single chip digital frequency synthesiser (1) for synthesising a frequency swept synthesised output signal of a selectable frequency sweep comprises a direct digital synthesiser (5) which produces the frequency swept synthesised output signal on an output terminal (7) in response to values of a frequency control digital word applied to a frequency control input (8) thereof by an on-chip data processing circuit (25). An on-chip programmable data storing circuit (12) is programmable to store data indicative of a selected mode in which the digital frequency synthesiser (1) is to operate, and to store data indicative of selectable frequency and the time domains of the frequency swept synthesised output signal to be produced. The data processing circuit (25) reads the mode of operation and the frequency domain data and if appropriate the time domain data of a frequency swept synthesised output signal to be produced by the digital frequency synthesiser (1) from the data storing circuit (12), and computes the values of the frequency control digital word and the sequence in which the values of the frequency control digital word are to be applied to the direct digital synthesiser (5). Depending on the mode of operation, the data processing circuit (25) determines the rate at which the values of the frequency control digital word are to be applied to the direct digital synthesiser (5) in response to a logic control signal applied to a control terminal (20) or as a function of a number of clock cycles of a system clock signal applied on a system clock terminal (10) or a number of cycles of the frequency swept synthesised output signal. The frequency swept synthesised output signal may also be produced in frequency bursts.

Abstract translation: 用于合成可选择频率扫描的频率扫描合成输出信号的单芯片数字频率合成器（1）包括直接数字合成器（5），其在输出端子（7）上产生频率扫描合成输出信号，响应于 由片上数据处理电路（25）施加到频率控制输入（8）的频率控制数字字。 片上可编程数据存储电路（12）可编程为存储指示数字频率合成器（1）将要工作的选定模式的数据，并存储表示频率扫描的可选择频率和时域的数据 合成输出信号。 数据处理电路（25）从数据存储电路（12）读取数字频率合成器（1）产生的频率扫描合成输出信号的时域数据和频域数据，如果合适的话， ，并且计算频率控制数字字的值和将频率控制数字字的值应用于直接数字合成器（5）的序列。 根据操作模式，数据处理电路（25）响应于施加到控制器的逻辑控制信号来确定将频率控制数字字的值应用于直接数字合成器（5）的速率 终端（20）或者作为施加在系统时钟端（10）上的系统时钟信号的时钟周期数或频率合成输出信号的周期数的函数。 频率扫描合成输出信号也可以在频率脉冲串中产生。

公开(公告)号：US07327816B2

公开(公告)日：2008-02-05

申请号：US10744037

申请日：2003-12-23

Applicant: Jason Messier

Inventor： Jason Messier

IPC: H04L7/00

CPC classification number: G06F1/0328 ,  G06F1/08

Abstract: An automatic test system using a DDS signal generator to create a signal with high spectral purity or a low jitter digital clock. The low jitter clock has variable frequency and is programmed to control other test functions, such as the generation of arbitrary waveforms. The DDS uses a high resolution, high sampling rate DAC to generate a sine wave that is converted to a digital clock. The architecture of the DDS signal generator allows low cost CMOS circuitry to be used to generate the data stream that feeds the high sample rate DAC.

Abstract translation: 使用DDS信号发生器创建具有高光谱纯度的信号或低抖动数字时钟的自动测试系统。 低抖动时钟具有可变频率，并被编程为控制其他测试功能，例如产生任意波形。 DDS使用高分辨率，高采样率DAC来产生转换为数字时钟的正弦波。 DDS信号发生器的架构允许使用低成本CMOS电路来产生馈送高采样率DAC的数据流。

公开(公告)号：US07248658B2

公开(公告)日：2007-07-24

申请号：US09968524

申请日：2001-10-02

Applicant: Filip Zalio

Inventor： Filip Zalio

IPC: H04L7/00

CPC classification number: G06F1/0328

Abstract: A clock generation circuit for a dual system radio frequency station is provided. The station includes a digital synthesis circuit clocked by a first clock signal for a first RF system that is adapted to generate a base signal output of a predetermined frequency. A second clock signal is derived from the sum of the frequency of the base signal and the frequency of the first clock signal.

Abstract translation: 提供了一种用于双系统射频站的时钟发生电路。 该站包括由适于产生预定频率的基本信号输出的第一RF系统的第一时钟信号时钟的数字合成电路。 第二时钟信号从基本信号的频率和第一时钟信号的频率之和导出。