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公开(公告)号：US07327816B2
公开(公告)日：2008-02-05
申请号：US10744037
申请日：2003-12-23
Applicant: Jason Messier
Inventor： Jason Messier
IPC: H04L7/00
CPC classification number: G06F1/0328 , G06F1/08
Abstract: An automatic test system using a DDS signal generator to create a signal with high spectral purity or a low jitter digital clock. The low jitter clock has variable frequency and is programmed to control other test functions, such as the generation of arbitrary waveforms. The DDS uses a high resolution, high sampling rate DAC to generate a sine wave that is converted to a digital clock. The architecture of the DDS signal generator allows low cost CMOS circuitry to be used to generate the data stream that feeds the high sample rate DAC.
Abstract translation: 使用DDS信号发生器创建具有高光谱纯度的信号或低抖动数字时钟的自动测试系统。 低抖动时钟具有可变频率，并被编程为控制其他测试功能，例如产生任意波形。 DDS使用高分辨率，高采样率DAC来产生转换为数字时钟的正弦波。 DDS信号发生器的架构允许使用低成本CMOS电路来产生馈送高采样率DAC的数据流。
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Patent Agency Ranking
公开(公告)号：US07523238B2
公开(公告)日：2009-04-21
申请号：US11170857
申请日：2005-06-30
Applicant: Jason Messier
Inventor： Jason Messier
CPC classification number: G06F17/5045
Abstract: By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.
Abstract translation: 通过减少在转换期间改变值的驱动器的累积数量，可以减少累积电流变化以及同时开关噪声效应。 此外，减小的累积电流变化还可以减小芯片的接地和/或电源平面中的电压波动，从而最小化由于电压骤降或峰值引起的潜在的不正确的逻辑功能。 在一个实现中，该方法包括读取第一字的第一组位的第一状态的值并获得第一组位中的每一个的第二状态的投影值。 如果可以通过改变第一组位的第二状态的投影值来减小第一开关噪声累积效应，则确定具有与第二状态的投影值不同的至少一个值的一组替代值，以减少 首先开关噪声累积效应。
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公开(公告)号：US20050135525A1
公开(公告)日：2005-06-23
申请号：US10744039
申请日：2003-12-23
Applicant: Jason Messier
Inventor： Jason Messier
CPC classification number: G06F1/0328 , H03L7/00
Abstract: A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock generated from the system clock. Accumulated phase error is reduced through the use of a parallel accumulator that tracks accumulated phase relative to the system clock. At coincidence points, the accumulated phase in the DDS accumulator is reset to the value in the system accumulator.
Abstract translation: 一种使用直接数字合成产生光谱纯，敏捷时钟的测试系统。 时钟用于自动测试系统中的模拟和数字仪器。 DDS电路与测试仪系统时钟同步，因为它是由系统时钟产生的DDS时钟计时的。 通过使用跟踪累积相位相对于系统时钟的并行累加器来减少累积相位误差。 在重合点，DDS累加器中的累加相复位为系统累加器中的值。
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公开(公告)号：US07336748B2
公开(公告)日：2008-02-26
申请号：US10744039
申请日：2003-12-23
Applicant: Jason Messier
Inventor： Jason Messier
IPC: H04L7/00
CPC classification number: G06F1/0328 , H03L7/00
Abstract: A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock generated from the system clock. Accumulated phase error is reduced through the use of a parallel accumulator that tracks accumulated phase relative to the system clock. At coincidence points, the accumulated phase in the DDS accumulator is reset to the value in the system accumulator.
Abstract translation: 一种使用直接数字合成产生光谱纯，敏捷时钟的测试系统。 时钟用于自动测试系统中的模拟和数字仪器。 DDS电路与测试仪系统时钟同步，因为它是由系统时钟产生的DDS时钟计时的。 通过使用跟踪累积相位相对于系统时钟的并行累加器来减少累积相位误差。 在重合点，DDS累加器中的累加相复位为系统累加器中的值。
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公开(公告)号：US20070005282A1
公开(公告)日：2007-01-04
申请号：US11170857
申请日：2005-06-30
Applicant: Jason Messier
Inventor： Jason Messier
CPC classification number: G06F17/5045
Abstract: By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.
Abstract translation: 通过减少在转换期间改变值的驱动器的累积数量，可以减少累积电流变化以及同时的开关噪声效应。 此外，减小的累积电流变化还可以减小芯片的接地和/或电源平面中的电压波动，从而最小化由于电压骤降或峰值引起的潜在的不正确的逻辑功能。 在一个实现中，该方法包括读取第一字的第一组位的第一状态的值并获得第一组位中的每一个的第二状态的投影值。 如果可以通过改变第一组位的第二状态的投影值来减小第一开关噪声累积效应，则确定具有与第二状态的投影值不同的至少一个值的一组替代值，以减少 首先开关噪声累积效应。
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公开(公告)号：US20050135524A1
公开(公告)日：2005-06-23
申请号：US10744037
申请日：2003-12-23
Applicant: Jason Messier
Inventor： Jason Messier
IPC: G01R31/3183 , G06F1/02 , G06F1/03 , H04L7/00
CPC classification number: G06F1/0328 , G06F1/08
Abstract: An automatic test system using a DDS signal generator to create a signal with high spectral purity or a low jitter digital clock. The low jitter clock has variable frequency and is programmed to control other test functions, such as the generation of arbitrary waveforms. The DDS uses a high resolution, high sampling rate DAC to generate a sine wave that is converted to a digital clock. The architecture of the DDS signal generator allows low cost CMOS circuitry to be used to generate the data stream that feeds the high sample rate DAC.
Abstract translation: 使用DDS信号发生器创建具有高光谱纯度的信号或低抖动数字时钟的自动测试系统。 低抖动时钟具有可变频率，并被编程为控制其他测试功能，例如产生任意波形。 DDS使用高分辨率，高采样率DAC来产生转换为数字时钟的正弦波。 DDS信号发生器的架构允许使用低成本CMOS电路来产生馈送高采样率DAC的数据流。
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