公开(公告)号：US20050263902A1

公开(公告)日：2005-12-01

申请号：US11174189

申请日：2005-07-01

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

IPC: H01L21/768 ,  H01L29/40 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L2221/1089

Abstract: A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.

公开(公告)号：US20050263891A1

公开(公告)日：2005-12-01

申请号：US11100912

申请日：2005-04-07

Applicant: Bih-Huey Lee ,  Hong-Yuan Chu ,  Ping-Kun Wu ,  Ching-Wen Lu ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Shing-Chyang Pan

Inventor： Bih-Huey Lee ,  Hong-Yuan Chu ,  Ping-Kun Wu ,  Ching-Wen Lu ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Shing-Chyang Pan

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76867

Abstract: A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying conductive layer such that the trenches have varying widths. The vias are lined with a first barrier layer. The first barrier layers along the bottom of vias are removed such that a recess formed in the underlying conductive layer. The recesses formed along the bottom of vias are such that the recess below narrower trenches is greater than the recess formed below wider trenches. In another embodiment, a second barrier layer may then be formed over the first barrier layer. In this embodiment, a portion of the conductive layer may be interposed between the first barrier layer and the second barrier layer.

Abstract translation: 提供了一种用于半导体器件的镶嵌结构。 在一个实施例中，镶嵌结构包括在通孔上形成的沟槽，其将沟槽电耦合到下面的导电层，使得沟槽具有变化的宽度。 通孔排列有第一阻挡层。 沿着通孔底部的第一阻挡层被去除，使得形成在下面的导电层中的凹陷。 沿着通孔底部形成的凹槽使得较窄沟槽下面的凹陷大于形成在较宽沟槽下方的凹陷。 在另一个实施例中，然后可以在第一阻挡层上形成第二阻挡层。 在该实施例中，导电层的一部分可插入在第一阻挡层和第二阻挡层之间。

公开(公告)号：US06864670B2

公开(公告)日：2005-03-08

申请号：US10442118

申请日：2003-05-21

Applicant: Jr-Hong Ouyang ,  Hui-Chuan Lai ,  Jing-Cheng Lin

Inventor： Jr-Hong Ouyang ,  Hui-Chuan Lai ,  Jing-Cheng Lin

IPC: H02M3/00 ,  H05K1/02 ,  G05F1/59

CPC classification number: H02M3/00 ,  H05K1/0216 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09663

Abstract: A method for eliminating noise interference and acoustic noise by a printed circuit board ground plane layout is disclosed. The method is applied to a circuit system having multiple outputs, wherein the circuit system has a first power converting module, a second power converting module and a printed circuit board. The first power converting module and the second power converting module respectively includes a first ground pin group and a second ground pin group. The method includes the steps of (a) connecting each ground pin of the first ground pin group to a respective solder point and connecting each solder point to a first node, and connecting each ground pin of the second ground pin group to a respective solder point and connecting each solder point to a second node, and (b) connecting the first node and the second node to a common node and connecting the common node to a solder point of a common ground terminal on the printed circuit board ground plane.

Abstract translation: 公开了一种通过印刷电路板接地平面布局消除噪声干扰和声学噪声的方法。 该方法应用于具有多个输出的电路系统，其中电路系统具有第一电力转换模块，第二电力转换模块和印刷电路板。 第一电力转换模块和第二电力转换模块分别包括第一接地引脚组和第二接地引脚组。 该方法包括以下步骤：（a）将第一接地引脚组的每个接地引脚连接到相应的焊点并将每个焊接点连接到第一节点，并将第二接地引脚组的每个接地引脚连接到相应的焊点 并且将每个焊接点连接到第二节点，以及（b）将所述第一节点和所述第二节点连接到公共节点，并将所述公共节点连接到所述印刷电路板接地层上的公共接地端子的焊接点。

公开(公告)号：US20050029665A1

公开(公告)日：2005-02-10

申请号：US10936922

申请日：2004-09-08

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L21/31 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract translation: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。

公开(公告)号：US06806192B2

公开(公告)日：2004-10-19

申请号：US10350837

申请日：2003-01-24

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L2144

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract translation: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。