公开(公告)号：US10080294B2

公开(公告)日：2018-09-18

申请号：US15846450

申请日：2017-12-19

Applicant: Japan Display Inc.

Inventor： Hideaki Abe ,  Yasushi Nakano ,  Hitoshi Kawaguchi ,  Ryouhei Suzuki

IPC: H05K1/18 ,  H05K5/00 ,  H05K1/11 ,  H01R4/04 ,  H01R12/62 ,  G02F1/1362 ,  G02F1/1345

CPC classification number: H05K1/189 ,  G02F1/1345 ,  G02F1/136286 ,  H01R4/04 ,  H01R12/62 ,  H01R2107/00 ,  H05K1/118 ,  H05K3/323 ,  H05K3/3442 ,  H05K3/361 ,  H05K2201/09663 ,  H05K2201/09918 ,  H05K2201/10136

Abstract: Terminal portions are arrayed at regular widths and regular intervals, and each face any enable terminal, and are electrically connected to the enable terminals by conductive particles. A lead portion is connected to the other terminal portion except for a pair of terminal portions which is a pair of terminal portions adjacent to each other, and extends from an overlap region to a lead region. A connection portion connects the respective terminal portions that are not connected with the lead portion to the adjacent terminal portions that are connected to the lead portion within an area of the overlap region. An interval between a pair of lead portions extending from a pair of connection portions located to sandwich a pair of terminal portions that are not connected with the lead portion therebetween is larger than an interval between the other adjacent lead portions.

公开(公告)号：US20180246601A1

公开(公告)日：2018-08-30

申请号：US15958388

申请日：2018-04-20

Applicant: Japan Display Inc.

Inventor： Hayato Kurasawa ,  Keisuke Asada ,  Tatsuya Ide ,  Koji Ishizaki

IPC: G06F3/044 ,  G06F3/041 ,  H05K1/02 ,  H05K1/14

CPC classification number: G06F3/044 ,  G02F1/13338 ,  G06F3/0412 ,  G06F2203/04108 ,  G06F2203/04112 ,  H05K1/028 ,  H05K1/117 ,  H05K1/147 ,  H05K3/28 ,  H05K3/361 ,  H05K2201/09263 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10128

Abstract: According to one embodiment, a detection device includes a substrate, detection electrode, terminal formed of a metal material, lead, coating layer, conductive adhesion layer, and circuit board. The lead connects the electrode and the terminal. The coating layer covers the electrode and the lead, and partly covers the terminal. The adhesion layer covers a part of the terminal exposed from the coating layer and covers a part of the coating layer. The circuit board is connected to the terminal with the adhesion layer interposed therebetween. At least in an overlapping area where the adhesion layer covers the coating layer, an area of the metal material per unit area is smaller than that of the other area of the terminal.

公开(公告)号：US20180103542A1

公开(公告)日：2018-04-12

申请号：US15724740

申请日：2017-10-04

Applicant: CANON KABUSHIKI KAISHA

Inventor： Masahiro Shinotsuka ,  Kazunori Miyake ,  Teruhiko Suzuki

IPC: H05K1/02 ,  H05K7/14 ,  G03G15/00

CPC classification number: H05K1/0259 ,  G03G15/80 ,  G03G21/1652 ,  H05K1/0215 ,  H05K1/0298 ,  H05K7/1422 ,  H05K2201/09663 ,  H05K2201/10409

Abstract: A printed circuit board for mounting on a support member, the printed circuit board including: a plurality of mounted portions for mounting the printed circuit board on the support member; a ground pattern configured to be electrically connected to the support member through the plurality of mounted portions; and a slit extended from a first mounted portion to a second mounted portion of the plurality of mounted portions and between a first portion, in which an electronic device is provided, of the ground pattern and a second portion, in which an electronic device is not provided, of the ground pattern.

公开(公告)号：US09871281B2

公开(公告)日：2018-01-16

申请号：US15587770

申请日：2017-05-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato

IPC: H01P3/08 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01P3/082 ,  H01P1/20363 ,  H01P3/084 ,  H01P3/085 ,  H05K1/0225 ,  H05K1/0242 ,  H05K1/115 ,  H05K1/147 ,  H05K2201/09618 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/0979

Abstract: A high-frequency signal line includes a dielectric body including a first dielectric layer and one or more other dielectric layers laminated together. A first signal line is provided on a first main surface, which is a main surface located on one side in a direction of lamination, of the first dielectric layer. A second signal line is provided on a second main surface, which is a main surface located on another side in the lamination direction, of the first dielectric layer so as to face the first signal line via the first dielectric layer. The second signal line is electrically connected to the first signal line. A first ground conductor is located on one side in the lamination direction than the first signal line. A second ground conductor is located on another side in the lamination direction than the second signal line.

公开(公告)号：US20170332476A1

公开(公告)日：2017-11-16

申请号：US15150834

申请日：2016-05-10

Applicant: Northrop Grumman Systems Corporation

Inventor： Charles M. Jackson ,  Elizabeth T. Kunkee

IPC: H05K1/02 ,  H01P3/08 ,  H01P3/06 ,  H05K1/14

CPC classification number: H05K1/025 ,  H01R12/523 ,  H01R12/714 ,  H01R13/2407 ,  H05K1/0222 ,  H05K1/0242 ,  H05K1/144 ,  H05K3/184 ,  H05K3/326 ,  H05K3/365 ,  H05K3/4015 ,  H05K3/4092 ,  H05K3/467 ,  H05K3/4679 ,  H05K2201/0311 ,  H05K2201/0397 ,  H05K2201/042 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/09809 ,  H05K2201/10257 ,  H05K2201/10378

Abstract: A resilient electrical connector assembly includes a base PCB and stacked layers of interconnected resilient conductive structures where each structure has at least two resilient conductive strips and at least two conductive contacts. One contact is integrated with a conductive path on the base PCB and another contact pad is positioned to establish a conductive path with a target PCB when the latter is mounted parallel to the base PCB. The resilient conductive strips flex due to a compressive force exerted between the base PCB and target PCB on the stacked layers. The resilient conductive structures are formed by depositing metal to sequentially form each of the stacked layers with one contact being initially formed in engagement with the conductive path on the base PCB.

公开(公告)号：US09748155B2

公开(公告)日：2017-08-29

申请号：US14897127

申请日：2014-07-09

Applicant: CANON KABUSHIKI KAISHA

Inventor： Tatsuo Nishino ,  Kiyoshi Sekiguchi

IPC: H05K1/14 ,  H01L23/13 ,  H04B15/00 ,  H05K1/11 ,  H05K1/18 ,  H05K7/14 ,  H05K7/18 ,  H05K9/00 ,  H05K1/02 ,  H05K3/34

CPC classification number: H01L23/13 ,  H01L2924/15311 ,  H04B15/005 ,  H05K1/0215 ,  H05K1/0224 ,  H05K1/0225 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/181 ,  H05K3/3442 ,  H05K9/0039 ,  H05K2201/09663 ,  Y02P70/611

Abstract: A printed wiring board includes a power supply conductor pattern arranged on one conductor layer, one ground conductor pattern arranged on the one conductor layer, and another ground conductor pattern arranged on the another conductor layer so as to be opposed to the power supply conductor pattern. The power supply conductor pattern includes a power supply pad on which a terminal of a capacitor is to be bonded. The one ground conductor pattern includes a ground pad on which another terminal of the capacitor is to be bonded. A slit is formed in the another ground conductor pattern so as to pass through a projection portion defined by projecting the power supply pad onto the another ground conductor pattern and divide a projection portion defined by projecting the power supply conductor pattern onto the another ground conductor pattern.

公开(公告)号：US20170212620A1

公开(公告)日：2017-07-27

申请号：US15483247

申请日：2017-04-10

Applicant: Japan Display Inc.

Inventor： Hayato Kurasawa ,  Keisuke Asada ,  Tatsuya Ide ,  Koji Ishizaki

IPC: G06F3/044 ,  H05K1/02 ,  H05K1/14 ,  G06F3/041

CPC classification number: G06F3/044 ,  G02F1/13338 ,  G06F3/0412 ,  G06F2203/04108 ,  G06F2203/04112 ,  H05K1/028 ,  H05K1/117 ,  H05K1/147 ,  H05K3/28 ,  H05K3/361 ,  H05K2201/09263 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10128

Abstract: According to one embodiment, a detection device includes a substrate, detection electrode, terminal formed of a metal material, lead, coating layer, conductive adhesion layer, and circuit board. The lead connects the electrode and the terminal. The coating layer covers the electrode and the lead, and partly covers the terminal. The adhesion layer covers a part of the terminal exposed from the coating layer and covers a part of the coating layer. The circuit board is connected to the terminal with the adhesion layer interposed therebetween. At least in an overlapping area where the adhesion layer covers the coating layer, an area of the metal material per unit area is smaller than that of the other area of the terminal.

公开(公告)号：US20170142836A1

公开(公告)日：2017-05-18

申请号：US14943299

申请日：2015-11-17

Applicant: Martin Brokner Christiansen ,  Leonard George Chorosinski ,  H. Craig Heffner ,  Stanley Katsuyoshi Wakamiya ,  Keith R. Kirkwood

Inventor： Martin Brokner Christiansen ,  Leonard George Chorosinski ,  H. Craig Heffner ,  Stanley Katsuyoshi Wakamiya ,  Keith R. Kirkwood

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/46 ,  H05K3/30 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/181 ,  H05K1/0203 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/303 ,  H05K3/46 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/09063 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/09763

Abstract: A circuit card assembly includes a substrate having longitudinally spaced first and second substrate end edges and transversely spaced top and bottom substrate surfaces. The top and/or bottom substrate surface has first, second, and third substrate regions. The first substrate region is directly laterally adjacent the first substrate side edge. The third substrate region is directly laterally adjacent the second substrate side edge. The second substrate region is located between the first and third substrate regions. At least one circuit trace is located on the selected substrate surface. The portion of the circuit trace in the first substrate region is made of only a first material. The portion of the circuit trace in the third substrate region is made of only a second material. The portion of the circuit trace in the second substrate region is made of both the first and second materials.

公开(公告)号：US20170094789A1

公开(公告)日：2017-03-30

申请号：US15255992

申请日：2016-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-won Park

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/113 ,  H05K1/0295 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/09663 ,  H05K2201/099 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A printed circuit board (PCB) is disclosed on which various kinds of electronic components having diverse specifications may be mounted. The PCB includes a substrate base a substrate base and a pad group formed on a surface of the substrate base. The pad group includes at least two pads. Each of the at least two pads includes a first sub-pad portion and a second sub-pad portion. The first sub-pad portion partially surrounds the second sub-pad portion. The second sub-pad portion of one of the at least two pads protrudes from an end portion of the first sub-pad portion toward another pad of the at least two pads.

公开(公告)号：US09600112B2

公开(公告)日：2017-03-21

申请号：US14511945

申请日：2014-10-10

Applicant: Apple Inc.

Inventor： Zhen Zhang ,  Paul S. Drzaic ,  Yi Tao

IPC: H05K1/02 ,  H05K1/03 ,  G06F1/16 ,  G06F3/041

CPC classification number: G06F3/0412 ,  G06F1/169 ,  G06F2203/04102 ,  H05K1/028 ,  H05K1/0281 ,  H05K1/0296 ,  H05K1/0393 ,  H05K2201/09263 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/10106

Abstract: A flexible substrate may have one or more bends. A bend in a flexible substrate may be made along a bend axis. Conductive traces in the flexible substrate may have elongated shapes. Each conductive trace may extend along a longitudinal axis that is perpendicular to the bend axis. Metal or other conductive materials may form the conductive traces. The traces may be formed from a chain of linked segments. Each segment may have patterned trace portions that surround one, two, or more than two openings. Traces may also be formed that have multiple layers of metal or other conductive material interconnected using vias. A polymer layer may cover the traces to align a neutral stress plane with the traces and to serve as a moisture barrier layer.