公开(公告)号：US20180294231A1

公开(公告)日：2018-10-11

申请号：US15945883

申请日：2018-04-05

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Hai Yang ZHANG ,  Cheng Long ZHANG ,  Xin JIANG

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/311

CPC分类号： H01L23/53276 ,  H01L21/28556 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2221/1094

摘要： Semiconductor device and fabrication method are provided. The method includes: providing a base substrate with a bottom metallic layer in the base substrate and a dielectric layer on the base substrate; forming interconnect openings through the dielectric layer and exposing the bottom metallic layer, where each interconnect openings includes a contacting hole and a groove on the contacting hole; forming a first conducting layer in the contacting hole, where the first conducting layer is made of a material having a first conductivity along a direction from the bottom metallic layer to a top surface of the first conducting layer; and after forming the first conducting layer, forming a second conducting layer in the groove, where the second conducting layer is made of a material having a second conductivity along a direction parallel to the top surface of the base substrate and the first conductivity is greater than the second conductivity.

公开(公告)号：US20180261503A1

公开(公告)日：2018-09-13

申请号：US15958568

申请日：2018-04-20

申请人： Entegris, Inc.

发明人： Shuang Meng ,  Richard Ulrich Assion ,  Thomas H. Baum ,  Bryan Clark Hendrix

IPC分类号： H01L21/768 ,  C23C16/455 ,  C23C16/02 ,  C23C16/40

CPC分类号： H01L21/76876 ,  C23C16/0272 ,  C23C16/14 ,  C23C16/28 ,  C23C16/405 ,  C23C16/45527 ,  H01L21/28061 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32051 ,  H01L21/76853 ,  H01L2221/1089

摘要： The disclosure relates to a method of making molybdenum films utilizing boron and molybdenum nucleation layers. The resulting molybdenum films have low electrical resistivity, are substantially free of boron, and can be made at reduced temperatures compared to conventional chemical vapor deposition processes that do not use the boron or molybdenum nucleation layers. The molybdenum nucleation layer formed by this process can protect the substrate from the etching effect of MoCl5 or MoOCl4, facilitates nucleation of subsequent CVD Mo growth on top of the molybdenum nucleation layer, and enables Mo CVD deposition at lower temperatures. The nucleation layer can also be used to control the grain sizes of the subsequent CVD Mo growth, and therefore controls the electrical resistivity of the Mo film.

公开(公告)号：US20180142345A1

公开(公告)日：2018-05-24

申请号：US15820640

申请日：2017-11-22

申请人： Entegris, Inc.

发明人： Shuang Meng ,  Richard Ulrich Assion ,  Thomas H. Baum ,  Bryan Clark Hendrix

IPC分类号： C23C16/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532

CPC分类号： C23C16/06 ,  C23C16/0272 ,  C23C16/0281 ,  C23C16/08 ,  H01L21/28061 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32051 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53257 ,  H01L2221/1089

摘要： The disclosure relates to a method of making molybdenum films utilizing boron and molybdenum nucleation layers. The resulting molybdenum films have low electrical resistivity, are substantially free of boron, and can be made at reduced temperatures compared to conventional chemical vapor deposition processes that do not use the boron or molybdenum nucleation layers. The molybdenum nucleation layer formed by this process can protect the substrate from the etching effect of MoCl5 or MoOCl4, facilitates nucleation of subsequent CVD Mo growth on top of the molybdenum nucleation layer, and enables Mo CVD deposition at lower temperatures. The nucleation layer can also be used to control the grain sizes of the subsequent CVD Mo growth, and therefore controls the electrical resistivity of the Mo film.

公开(公告)号：US09938622B2

公开(公告)日：2018-04-10

申请号：US15045667

申请日：2016-02-17

申请人： Applied Materials, Inc.

发明人： Tae Hong Ha ,  Sang Ho Yu ,  Kiejin Park

IPC分类号： C23C16/06 ,  C23C16/50 ,  C23C16/46 ,  C23C16/505 ,  C23C16/02 ,  C23C16/16 ,  C23C16/18 ,  C23C28/00 ,  H01L21/285 ,  H01L21/768 ,  C23C16/513

CPC分类号： C23C16/46 ,  C23C16/0281 ,  C23C16/16 ,  C23C16/18 ,  C23C16/505 ,  C23C16/513 ,  C23C28/322 ,  C23C28/34 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/76873 ,  H01L2221/1089

摘要： Methods for depositing ruthenium by a PECVD process are described herein. Methods for depositing ruthenium can include positioning a substrate in a processing chamber, the substrate having a barrier layer formed thereon, heating and maintaining the substrate at a first temperature, flowing a first deposition gas into a processing chamber, the first deposition gas comprising a ruthenium containing precursor, generating a plasma from the first deposition gas to deposit a first ruthenium layer over the barrier layer, flowing a second deposition gas into the processing chamber to deposit a second ruthenium layer over the first ruthenium layer, the second deposition gas comprising a ruthenium containing precursor, depositing a copper seed layer over the second ruthenium layer and annealing the substrate at a second temperature.

公开(公告)号：US20180019165A1

公开(公告)日：2018-01-18

申请号：US15649248

申请日：2017-07-13

申请人： Entegris, Inc.

发明人： Thomas H. Baum ,  Philip S.H. Chen ,  Robert Wright ,  Bryan Hendrix ,  Shuang Meng ,  Richard Assion

IPC分类号： H01L21/768 ,  H01L21/285 ,  C23C16/06

CPC分类号： H01L21/76876 ,  C23C16/0272 ,  C23C16/045 ,  C23C16/06 ,  C23C16/14 ,  C23C16/45553 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L2221/1089

摘要： A method of forming a molybdenum-containing material on a substrate is described, in which the substrate is contacted with molybdenum oxytetrachloride (MoOCl4) vapor under vapor deposition conditions, to deposit the molybdenum-containing material on the substrate. In various implementations, a diborane contact of the substrate may be employed to establish favorable nucleation conditions for the subsequent bulk deposition of molybdenum, e.g., by chemical vapor deposition (CVD) techniques such as pulsed CVD.

公开(公告)号：US20180012842A1

公开(公告)日：2018-01-11

申请号：US15704568

申请日：2017-09-14

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： CHENGLONG ZHANG ,  HAIYANG ZHANG

IPC分类号： H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5283 ,  H01L21/32136 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings.

公开(公告)号：US20160079176A1

公开(公告)日：2016-03-17

申请号：US14656542

申请日：2015-03-12

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Atsunobu ISOBAYASHI ,  Masayuki KITAMURA ,  Yuichi YAMAZAKI ,  Akihiro KAJITA ,  Tatsuro SAITO ,  Taishi ISHIKURA ,  Atsuko SAKATA ,  Tadashi SAKAI ,  Makoto WADA

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/033

CPC分类号： H01L23/53276 ,  H01L21/76838 ,  H01L21/76876 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a first film having a first melting point, forming a pattern of a second film on an upper surface of the first film, the second film having a second melting point lower than the first melting point, and forming a graphene film on the upper surface of the first film, the graphene film being formed from a side surface of the pattern of the second film.

摘要翻译： 根据一个实施例，一种制造半导体器件的方法，该方法包括：形成具有第一熔点的第一膜，在第一膜的上表面上形成第二膜的图案，第二膜具有第二熔点 低于第一熔点，并且在第一膜的上表面上形成石墨烯膜，所述石墨烯膜由第二膜的图案的侧表面形成。

公开(公告)号：US09269615B2

公开(公告)日：2016-02-23

申请号：US13554020

申请日：2012-07-20

申请人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

发明人： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76873 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a recess in a dielectric layer of a substrate. An adhesion barrier layer is formed to line the recess. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. The recess is filled with a fill layer.

摘要翻译： 形成互连结构的方法包括在基板的电介质层中形成凹部。 形成粘合阻挡层以使凹部成线。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 该凹部填充有填充层。

公开(公告)号：US09209134B2

公开(公告)日：2015-12-08

申请号：US13904360

申请日：2013-05-29

申请人： Intermolecular, Inc.

发明人： Mankoo Lee

IPC分类号： H01L21/768 ,  H01L23/532 ,  C23C16/04 ,  C23C16/455

CPC分类号： H01L23/53238 ,  C23C16/04 ,  C23C16/45544 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods to increase metal interconnect reliability are provided. Methods include forming a conformal barrier layer within an opening in a semiconductor device structure and forming a copper alloy material above the conformal barrier layer. Next, removing the copper alloy material that extends beyond the opening. Removing native oxide from a top surface of the copper alloy material. Further, annealing or applying a plasma treatment to the copper alloy material. Finally, forming a capping layer above the copper alloy material. Notably, near the top of the copper alloy material, smaller copper grain growth may be present. Furthermore, more non-copper alloy atoms are present near the top of the copper alloy material than the bulk of the copper alloy material.

摘要翻译： 提供了提高金属互连可靠性的方法。 方法包括在半导体器件结构的开口内形成保形阻挡层，并在保形阻挡层之上形成铜合金材料。 接下来，去除延伸超过开口的铜合金材料。 从铜合金材料的顶面去除原生氧化物。 此外，对铜合金材料退火或进行等离子体处理。 最后，在铜合金材料上方形成覆盖层。 值得注意的是，在铜合金材料的顶部附近，可能存在较小的铜晶粒生长。 此外，在铜合金材料的顶部附近存在比铜合金材料的主体更多的非铜合金原子。

公开(公告)号：US20150348826A1

公开(公告)日：2015-12-03

申请号：US14292385

申请日：2014-05-30

申请人： APPLIED MATERIALS, INC.

发明人： Roey Shaviv ,  Ismail T. Emesh ,  Dimitrios Argyris

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53238 ,  C25D3/38 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： In accordance with one embodiment of the present disclosure, a method for depositing metal on a reactive metal film on a workpiece includes obtaining a workpiece including a dielectric surface; forming a barrier layer on the dielectric surface; depositing a seed layer on the barrier layer, wherein the barrier and seed stack includes at least one metal having a standard electrode potential of less than 0.34 V; and depositing a metallization layer on the seed layer using a diluted acid bath in a pH range of about 1 to about 5 and a current density in the range of about 10 mA/cm2 to about 30 mA/cm2.

摘要翻译： 根据本公开的一个实施例，用于在工件上的反应性金属膜上沉积金属的方法包括获得包括电介质表面的工件; 在电介质表面上形成阻挡层; 在阻挡层上沉积种子层，其中所述势垒和种子堆叠包括至少一种具有小于0.34V的标准电极电位的金属; 以及使用在约1至约5的pH范围内的电流密度和约10mA / cm 2至约30mA / cm 2范围内的电流密度的稀酸浴，在种子层上沉积金属化层。