公开(公告)号：US09983262B1

公开(公告)日：2018-05-29

申请号：US15198217

申请日：2016-06-30

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Dan Trock ,  Ron Diamant

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/31724 ,  G01R31/3177 ,  G01R31/318525 ,  G01R31/31853 ,  G01R31/3187

Abstract: A device includes one or more random number generator (RNG) cores (e.g., true random number generator cores) and a built-in self-test controller (BIST) configured to perform various fault tests on each RNG core. The tests include a stuck-at-1 fault test, a stuck-at-0 fault test, and a transition delay fault test. For those RNG cores that have multiple ring oscillators, each individual ring oscillator is fault tested by the BIST controller. For those RNG cores that have a multi-tap inverter chain configuration, the individual taps may be tested by the BIST controller. The RNG core also may comprise a bi-stable cell which can be tested by the BIST controller as well.

公开(公告)号：US09973205B1

公开(公告)日：2018-05-15

申请号：US15633345

申请日：2017-06-26

Applicant: Amazon Technologies, Inc.

Inventor： Ori Weber ,  Ron Diamant ,  Yair Sandberg

IPC: H03M7/34 ,  H03M7/30 ,  G06T9/00 ,  G06T3/40

CPC classification number: H03M7/3086 ,  G06T3/40 ,  G06T9/005 ,  H03M7/30 ,  H03M7/55 ,  H03M7/6005 ,  H03M7/6064

Abstract: The following description is directed to decompression using cascaded history buffers. In one example, an apparatus can include a decompression pipeline configured to decompress compressed data comprising code words that reference a history of decompressed data generated from the compressed data. The apparatus can include a first-level history buffer configured to store a more recent history of the decompressed data received from the decompression pipeline. The apparatus can include a second-level history buffer configured to store a less recent history of the decompressed data received from the first-level history buffer.

公开(公告)号：US09747219B1

公开(公告)日：2017-08-29

申请号：US15053994

申请日：2016-02-25

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Noam Efraim Bashari ,  Ron Diamant ,  Yaniv Shapira ,  Barak Wasserstrom

IPC: G06F12/10 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/10 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/067 ,  G06F13/16 ,  G06F13/4068 ,  G06F2212/1016

Abstract: An apparatus such as a system-on-a-chip includes memory that is distributed through multiple functional hardware circuits. Each functional hardware circuit includes memory, and each functional hardware circuit can be configured to have its memory used either by the respective functional hardware circuit or by the apparatus' master device (e.g., main processor). For those functional hardware circuits that are not needed for a given application, their memories can be repurposed for use by the master device. Related methods are also disclosed.

公开(公告)号：US20170242870A1

公开(公告)日：2017-08-24

申请号：US15590898

申请日：2017-05-09

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Leah Shalev ,  Erez Izenberg ,  Georgy Machulsky ,  Ron Diamant

IPC: G06F17/30

CPC classification number: G06F16/1752 ,  G06F16/27 ,  G06F16/9014

Abstract: A method for in-band de-duplication, the method may include receiving by a hardware accelerator, a received packet of a first sequence of packets that conveys a first data chunk; applying a data chunk hash calculation process on the received packet while taking into account a hash calculation result obtained when applying the data chunk hash calculation process on a last packet of the first sequence that preceded the received packet; wherein the calculating of the first data chunk hash value is initiated before a completion of a reception of the entire first data chunk by the hardware accelerator.