公开(公告)号：US09983851B1

公开(公告)日：2018-05-29

申请号：US15274844

申请日：2016-09-23

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Michael Baranchik ,  Svetlana Kantorovych ,  Ori Weber

IPC: G06F7/72

CPC classification number: G06F7/727

Abstract: A hardware circuit computes a checksum using a technique such as the Adler-32 checksum algorithm. The hardware circuit may include one or more serially-connected chains of adders followed by a modulus circuit. The modulus circuit produces a modulus value in N, where N is not an integer power of 2. In some examples, N is 65,521. In some examples, the modulus circuit may produce a modulus value modulo 216 and then correct that value to modulo N. In other examples, the modulus circuit may include selection logic that selects an appropriate integer multiple of 65,521 to determine the modulo 65,521 result directly.

公开(公告)号：US09880960B1

公开(公告)日：2018-01-30

申请号：US14869775

申请日：2015-09-29

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Ori Weber ,  Omer Shaked

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4221

Abstract: A configurable sponge function engine. The configurable engine includes a state register having bitrate and capacity sections, each having a variable size, where a sum of the bitrate and capacity sizes is fixed. A controller generates a bitrate size indication. A configurable message processor receives an input message from an input bus, receives the size indication, fragments the input message into fragmented blocks of a size specified by the size indication, and converts the blocks to a bus width of the bitrate and capacity sizes. An iterative calculator receives the blocks, performs iterative processing operations on the blocks, and stores a result of each operation in the state register overwriting a previous register value. An output adaptor receives a value stored in the state register after the block corresponding to the end of the input message is processed and outputs the register value converted to have an output bus width.

公开(公告)号：US10747700B1

公开(公告)日：2020-08-18

申请号：US15832546

申请日：2017-12-05

Applicant: Amazon Technologies, Inc.

Inventor： Adiel Sarusi ,  Ron Diamant ,  Ori Weber ,  Erez Izenberg

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: Techniques disclosed herein relate to dynamically configurable multi-stage pipeline processing units. In one embodiment, a circuit includes a plurality of processing engines and a plurality of switches. Each of the plurality of processing engines includes an input port and an output port. Each of the plurality of switches comprises two input ports and two output ports. For each processing engine, the input port of the processing engine is electrically coupled to one of the switches, the output port of the processing engine is electrically coupled to another one of the switches, and the input port of the processing engine is electrically coupled to the output port of each of the processing engines by the switches.

公开(公告)号：US09698819B1

公开(公告)日：2017-07-04

申请号：US15390304

申请日：2016-12-23

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Michael Baranchik ,  Ron Diamant ,  Muhannad Ghanem ,  Ori Weber

IPC: H03M7/40 ,  H03M7/30 ,  H03M7/42

CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M7/405 ,  H03M7/42 ,  H03M7/6076

Abstract: A method for generating Huffman codewords to encode a dataset includes selecting a Huffman tree type from a plurality of different Huffman tree types. Each of the Huffman tree types specifies a different range of codeword length in a Huffman tree. A Huffman tree of the selected type is produced by: determining a number of nodes available to be allocated as leaves in each level of the Huffman tree accounting for allocation of leaves in each level of the Huffman tree; allocating nodes to be leaves such that the number of nodes allocated in a given level of the Huffman tree is constrained to be no more than the number of nodes available to be allocated in the given level; and assigning the leaves to symbols of the dataset based an assignment strategy selected from a plurality of assignment strategies to produce symbol codeword information.

公开(公告)号：US10929584B1

公开(公告)日：2021-02-23

申请号：US16712933

申请日：2019-12-12

Applicant: Amazon Technologies, Inc.

Inventor： Benzi Denkberg ,  Uri Leder ,  Ori Weber

IPC: G06F30/33 ,  G06F5/06 ,  G06F30/3323

Abstract: Environmental modification testing with a formal verification is implemented for language-specified hardware designs. A language-specified hardware design may be received. A reference copy of the language-specified hardware design may be created. A formal verification may be performed on both the language-specified hardware design and the reference copy with a same input data. Different environmental assumptions for processing the same input data through the reference copy and the language-specified hardware design may be applied. An output value of the language-specified hardware design may be compared with an output value of the reference copy to determine whether those output values match. Error indications may be provided based on a result of the comparison.

公开(公告)号：US10387350B1

公开(公告)日：2019-08-20

申请号：US15851450

申请日：2017-12-21

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Ori Weber ,  Omer Shaked

IPC: G06F13/40 ,  G06F13/42

Abstract: A configurable sponge function engine. The configurable engine includes a register having bitrate and capacity sections, each having a variable size, where a sum of the bitrate and capacity sizes is fixed. A controller generates a bitrate size indication. A configurable message processor receives an input message from an input bus, receives the size indication, fragments the input message into fragmented blocks of a size specified by the size indication, and converts the blocks to a bus width of the bitrate and capacity sizes. An iterative calculator receives the blocks, performs iterative processing operations on the blocks, and stores a result of each operation in the register overwriting a previous register value. An output adaptor receives a value stored in the register after the block corresponding to the end of the input message is processed and outputs the register value converted to have an output bus width.

公开(公告)号：US10187081B1

公开(公告)日：2019-01-22

申请号：US15633506

申请日：2017-06-26

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Ori Weber

IPC: H03M7/34 ,  H03M7/30

Abstract: Disclosed herein are techniques for improving compression ratio for dictionary-based data compression. A method includes receiving a data block to be compressed, selecting an initial compression dictionary from a plurality of initial compression dictionaries based on a characteristic of the data block, loading the initial compression dictionary into an adaptive compression dictionary in a buffer, and compressing the data block using the adaptive compression dictionary. The method also includes updating the adaptive compression dictionary based on data in the data block that has been compressed, while compressing the data block.

公开(公告)号：US10168909B1

公开(公告)日：2019-01-01

申请号：US15084013

申请日：2016-03-29

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Svetlana Kantorovych ,  Georgy Machulsky ,  Ori Weber ,  Nafea Bshara

IPC: G06F11/34 ,  G06F3/06

Abstract: Described herein are techniques for providing data compression and decompression within the bounds of hardware constraints. In some embodiments, the disclosure provides that a processing entity may load a portion of a data stream into a memory buffer. In some embodiments, the size of the portion of data loaded into the memory buffer may be determined based on a capacity of the memory buffer. The processing entity may determine whether the portion of data loaded into the memory buffer includes matching data segments. Upon determining that the portion of data does not include matching data segments, the processing entity may generate a sequence that includes uncompressed data and an indication that the sequence contains no matching data segments.

公开(公告)号：US20180375528A1

公开(公告)日：2018-12-27

申请号：US15976312

申请日：2018-05-10

Applicant: Amazon Technologies, Inc.

Inventor： Ori Weber ,  Ron Diamant ,  Yair Sandberg

IPC: H03M7/30 ,  G06T9/00 ,  G06T3/40

Abstract: The following description is directed to decompression using cascaded history buffers. In one example, an apparatus can include a decompression pipeline configured to decompress compressed data comprising code words that reference a history of decompressed data generated from the compressed data. The apparatus can include a first-level history buffer configured to store a more recent history of the decompressed data received from the decompression pipeline. The apparatus can include a second-level history buffer configured to store a less recent history of the decompressed data received from the first-level history buffer.

公开(公告)号：US10020819B1

公开(公告)日：2018-07-10

申请号：US15718669

申请日：2017-09-28

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Michael Baranchik ,  Ori Weber

IPC: H03M7/40 ,  H03M7/30

CPC classification number: H03M7/6005 ,  H03M7/3084 ,  H03M7/4037 ,  H03M7/60 ,  H03M7/6017 ,  H03M7/6023

Abstract: A computing system includes a network interface, a processor, and a decompression circuit. In response to a compression request from the processor the decompression circuit compresses data to produce compressed data and transmits the compressed data through the network interface. In response to a decompression request from the processor for compressed data the decompression circuit retrieves the requested compressed data, speculatively detects codewords in each of a plurality of overlapping bit windows within the compressed data, selects valid codewords from some, but not all of the overlapping bit windows, decodes the selected valid codewords to generate decompressed data, and provides the decompressed data to the processor.