公开(公告)号：US07251147B1

公开(公告)日：2007-07-31

申请号：US11146639

申请日：2005-06-07

Applicant: Dinesh Maheshwari

Inventor： Dinesh Maheshwari

IPC: G11C15/00 ,  G11C7/00

CPC classification number: G11C15/00

Abstract: A content comparator memory (CCM) device can include a row (100) of CCM cells (102-1 to 102-I). Each CCM cell (102-1 to 102-I) can have a controllable signal path (104-1 to 104-I) arranged in series to form a match path (106) that provides a match indication MATCH that can be activated when a comparand value (CD[1:I]) is determined to match a stored data value. Each CCM cell (102-1 to 102-I) can also be commonly connected to a comparator line (110) that can provide a comparator indication CMP when a compare value (CD[1:I]) has a predetermined magnitude with respect to a stored value.

Abstract translation: 内容比较器存储器（CCM）设备可以包括CCM单元（102-1至102-I）的行（100）。 每个CCM单元（102-1至102-I）可以具有串联布置的可控信号路径（104-1至104-I），以形成匹配路径（106），该匹配路径（106）提供匹配指示MATCH，其可以在 确定比较值（CD [1：I]）以匹配存储的数据值。 每个CCM单元（102-1至102-I）也可以共同地连接到比较器线（110），当比较值（CD [1：I]）相对于 存储值。

公开(公告)号：US07206212B1

公开(公告)日：2007-04-17

申请号：US10217746

申请日：2002-08-13

Applicant: Richard K. Chou

Inventor： Richard K. Chou

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) (200) is disclosed that includes a value match mode, where a comparand value can be compared to a masked data value, and a range match mode where a comparand value can be compared to an upper range limit UR and a lower range limit LR. The CAM (200) may include a number of CAM cells (204-n to 204-0) that may each be connected to a compare section (109). A compare section (109) can include a first compare circuit (210) that may generate a match indication on a match line (212) and a second compare circuits (214-n to 214-0). A more significant second compare circuits (214-n) may provide upper and lower limit match results (UMn, LMn) to a less significant first compare circuit (210).

Abstract translation: 公开了一种内容可寻址存储器（CAM）（200），其包括值匹配模式，其中可以将比较值与掩蔽的数据值进行比较，以及范围匹配模式，其中比较值可以与上限范围UR 和下限范围LR。 CAM（200）可以包括可以各自连接到比较部分（109）的多个CAM单元（204-n至204-0）。 比较部分（109）可以包括可以在匹配线（212）和第二比较电路（214-n至214-0）上生成匹配指示的第一比较电路（210）。 更重要的第二比较电路（214-n）可以向较不重要的第一比较电路（210）提供上限和下限匹配结果（UMn，LMn）。

公开(公告)号：US07171595B1

公开(公告)日：2007-01-30

申请号：US10156532

申请日：2002-05-28

Applicant: Charles C. Huse ,  Bindiganavale S. Nataraj ,  Kumaresh Kavedi

Inventor： Charles C. Huse ,  Bindiganavale S. Nataraj ,  Kumaresh Kavedi

IPC: G11C29/00

CPC classification number: G11C29/12 ,  G11C15/00

Abstract: According to one embodiment of the present invention, a content addressable memory (CAM) device includes a CAM array that includes a plurality of rows of CAM cells each coupled to a corresponding match line, and a test circuit coupled to the match lines that outputs row match results from the match lines onto a match output.

Abstract translation: 根据本发明的一个实施例，内容可寻址存储器（CAM）装置包括CAM阵列，其包括多个CAM单元阵列，每个CAM单元耦合到对应的匹配线，以及耦合到输出行的匹配线的测试电路 将匹配行的结果与匹配输出进行匹配。

公开(公告)号：US07154764B2

公开(公告)日：2006-12-26

申请号：US11101873

申请日：2005-04-09

Applicant: Bindiganavale S. Nataraj

Inventor： Bindiganavale S. Nataraj

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A bit line control circuit is coupled between a bit line of an associated Content Addressable Memory (CAM) Array and a supply voltage. The bit line control circuit adjusts the charge current for the bit line in response to a bit line control signal. For some embodiments, the bit line control circuit includes a dynamic component and a static component to control the bit line.

Abstract translation: 位线控制电路耦合在相关联的内容可寻址存储器（CAM）阵列的位线和电源电压之间。 位线控制电路响应于位线控制信号调整位线的充电电流。 对于一些实施例，位线控制电路包括用于控制位线的动态分量和静态分量。

公开(公告)号：US07117301B1

公开(公告)日：2006-10-03

申请号：US10329246

申请日：2002-12-23

Applicant: David V. James ,  Jagadeesan Rajamanickam

Inventor： David V. James ,  Jagadeesan Rajamanickam

IPC: G06F12/00

CPC classification number: G11C15/00 ,  G06F17/30949

Abstract: A search engine system (100) and CAM device (300) are disclosed. A search engine system (100) may generate response packets (112) in response to requests packets (110) and include at least one content addressable memory (CAM) device (102-0) having an input interface (116-0) for receiving data packets and an output interface (116-1) for transmitting data packets.

Abstract translation: 公开了搜索引擎系统（100）和CAM设备（300）。 搜索引擎系统（100）可以响应于请求分组（110）生成响应分组（112），并且包括具有用于接收的输入接口（116-0）的至少一个内容可寻址存储器（CAM）设备（102- 0） 数据分组和用于发送数据分组的输出接口（116-1）。

公开(公告)号：US07110408B1

公开(公告)日：2006-09-19

申请号：US09815921

申请日：2001-03-24

Applicant: Bindiganavale S. Nataraj

Inventor： Bindiganavale S. Nataraj

IPC: H04L12/28 ,  G06F12/00 ,  G06F13/00

CPC classification number: H03K3/356139 ,  G11C8/04 ,  G11C15/04 ,  H03K23/56

Abstract: A digital signal processor. The digital signal processor includes a content addressable memory (CAM) array for storing entries. The digital signal processor includes a partitioned priority index table having a plurality of rows and columns of priority blocks. Each row of the plurality of rows of priority blocks is capable of storing a priority number associated with an entry in the CAM array. Each column of the plurality of columns of priority blocks has compare logic coupled to each of the priority blocks in its respective column. The digital signal processor includes an encoder coupled to the partitioned priority index table.

Abstract translation: 数字信号处理器。 数字信号处理器包括用于存储条目的内容可寻址存储器（CAM）阵列。 数字信号处理器包括具有多个优先权块的行和列的分区优先级索引表。 多行优先级块的每行能够存储与CAM阵列中的条目相关联的优先权号码。 多列优先级块中的每一列具有耦合到其相应列中每个优先级块的比较逻辑。 数字信号处理器包括耦合到分区优先级索引表的编码器。

公开(公告)号：US07043673B1

公开(公告)日：2006-05-09

申请号：US10002713

申请日：2001-11-01

Applicant: Michael E. Ichiriu ,  Varadarajan Srinivasan

Inventor： Michael E. Ichiriu ,  Varadarajan Srinivasan

IPC: G11C29/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) device having circuitry to generate a biased sequence of addresses. A first counter circuit increments an address value in response to a clock signal and resets the address value to a start address in response to a control signal. A second counter increments a limit value in response to a control signal. A compare circuit compares the address value and the limit value and, if the address value and the limit value have a predetermined relationship, asserts the control signal.

Abstract translation: 一种内容可寻址存储器（CAM）装置，具有产生偏置的地址序列的电路。 第一计数器电路响应于时钟信号递增地址值，并且响应于控制信号将地址值重置为起始地址。 第二计数器响应于控制信号而增加极限值。 比较电路比较地址值和极限值，并且如果地址值和限制值具有预定关系，则断言控制信号。

公开(公告)号：US06993622B2

公开(公告)日：2006-01-31

申请号：US10077829

申请日：2002-02-15

Applicant: Sandeep Khanna ,  Ramagopal R. Madamala

Inventor： Sandeep Khanna ,  Ramagopal R. Madamala

IPC: G06F12/00

CPC classification number: H04L29/06 ,  G11C15/00 ,  H04L45/7453 ,  H04L69/22

Abstract: An apparatus and method for generating a comparand in a content addressable memory array. The apparatus includes a content addressable memory (CAM) array and translation circuitry to receive translation information indicative of translation of a bit group from an initial position in input data to a different position in a comparand transmitted to the CAM array. The translation circuitry includes a switch circuit, one or more storage elements to store the translation information, and one or more decode circuitry to decode the translation information and establish switch circuit connections between the initial position and the position in the comparand. The apparatus also includes program circuitry to provide a bit level programming interface with the translation circuitry. The apparatus may also include a programming bit register to store programming information in the form of a binary pattern where each bit represents a bit group of the input data.

公开(公告)号：US06978343B1

公开(公告)日：2005-12-20

申请号：US10213244

申请日：2002-08-05

Applicant: Michael E. Ichiriu

Inventor： Michael E. Ichiriu

IPC: G06F12/00 ,  G11C15/00

CPC classification number: G11C15/00 ,  G11C2029/0409

Abstract: A content addressable memory (CAM) device having an error correction function. The CAM device includes an array of CAM cells, row parity storage elements and column parity storage elements. The row parity storage elements store row parity values that correspond to contents of respective rows of the CAM cells, and the column parity storage elements store column parity values that correspond to respective columns of the CAM cells. A bit error in the array is detected through row and column parity checking that uniquely identifies the row and column location of the error and enables correction of the error.

Abstract translation: 一种具有纠错功能的内容寻址存储器（CAM）装置。 CAM设备包括CAM单元阵列，行奇偶校验存储元件和列奇偶校验存储元件。 行奇偶校验存储元件存储与CAM单元的各行的内容对应的行奇偶校验值，列奇偶校验存储元件存储与CAM单元的各列对应的列奇偶校验值。 通过行和列奇偶校验检测来检测阵列中的位错误，唯一地标识错误的行和列位置，并能够纠正错误。

公开(公告)号：US06944040B1

公开(公告)日：2005-09-13

申请号：US10938028

申请日：2004-09-10

Applicant: Sandeep Khanna

Inventor： Sandeep Khanna

IPC: G11C7/10 ,  G11C15/00 ,  H03K5/00 ,  H03K5/15

CPC classification number: G11C7/106 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C15/00 ,  H03K5/1508 ,  H03K2005/00058

Abstract: An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and generate the delayed clock signal using one or more delay elements.

Abstract translation: 一种具有耦合到内容可寻址存储器（CAM）阵列的输出寄存器的装置。 输出寄存器可以被配置为基于延迟的时钟信号输出数据。 可编程延迟电路可以被耦合以接收参考时钟信号并且使用一个或多个延迟元件产生延迟的时钟信号。