-
公开(公告)号：US20040057538A1
公开(公告)日：2004-03-25
申请号：US10618073
申请日：2003-07-11
IPC: H04B001/10
CPC classification number: H04B1/7117 , H04B2201/70707
Abstract: A low-power receiver architecture of use in direct sequence spread spectrum communications system receivers, such as in a code division multiple access system, is provided. The receiver employs analog correlation, wherein its analog-digital, converters are able to operate at the system symbol rate, and the requirement for finite impulse response filters is obviated. The low-power receiver architecture is also applicable as a front-end structure for multiple-mode receivers.
Abstract translation: 提供了一种在直接序列扩频通信系统接收机中使用的低功率接收机架构，例如在码分多址系统中。 接收机采用模拟相关，其中模拟数字转换器能够以系统符号速率运行，并且消除了对有限脉冲响应滤波器的要求。 低功耗接收机架构也适用于多模接收机的前端结构。
-
252.发明申请Memory transfer controller and method of transfer control of video line data and macroblock data 有权存储器传输控制器和视频行数据和宏块数据的传输控制方法公开(公告)号：US20030169371A1
公开(公告)日：2003-09-11
申请号：US10356719
申请日：2003-01-30
Applicant: STMicroelectronics Asia Pacific Pte. Ltd.
Inventor： Patricia Wei Yin Chiang , Lucas Y.W. Hui
IPC: H04N009/455
CPC classification number: H04N19/423 , H04N19/61
Abstract: A method of transferring sets of video line data and macroblock data, comprising the steps of determining a macroblock period and a video line period longer than the macroblock period, dividing each set of video line data to be transferred within the video line period into two or more portions according to the difference between the determined macroblock period and video line period, aligning a burst transfer of each of the portions of the divided set of video line data and each set of macroblock data to the macroblock period, and initiating the burst transfer of the sets of video line data and macroblock data at macroblock period intervals.
Abstract translation: 一种传输视频行数据和宏块数据集的方法，包括以下步骤：确定比宏块周期长的宏块周期和视频行周期，将在视频行周期内传送的每组视频行数据划分成两个或 根据所确定的宏块周期和视频行周期之间的差异来更多部分，将分割的视频行数据集合的每个部分的突发传送与每个宏块数据集对齐到宏块周期，并且发起突发传送 在宏块周期间隔的视频行数据和宏块数据集合。
-
公开(公告)号：US12255595B2
公开(公告)日：2025-03-18
申请号：US17371368
申请日：2021-07-09
Inventor： Marco Sautto , Giona Fucili , Valerio Lo Muzzo , Kaufik Linggajaya
Abstract: In accordance with an embodiment, a method of operating a piezoelectric transducer configured to transduce mechanical vibrations into transduced electrical signals at a pair of sensor electrodes includes stimulating a resonant oscillation of the piezoelectric transducer by applying at least one pulse electrical stimulation signal to the pair of sensor electrodes; detecting, at the pair of sensor electrodes, at least one electrical signal resulting from the stimulated resonant oscillation, wherein the at least one electrical signal resulting from the stimulated resonant oscillation oscillates at a resonance frequency of the piezoelectric transducer; measuring a frequency of oscillation of the at least one electrical signal resulting from the stimulated resonant oscillation to obtain a measured resonance frequency of the piezoelectric transducer; and tuning a stopband frequency of a notch filter coupled to the piezoelectric transducer to match the measured resonance frequency of the piezoelectric transducer.
-
公开(公告)号：US12149094B2
公开(公告)日：2024-11-19
申请号：US17490437
申请日：2021-09-30
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Chee Weng Cheong , Kien Beng Tan
IPC: H02J3/32 , G01R19/165 , H02J7/04 , H02J50/10 , H02J50/90 , H02M1/00 , H02M3/156 , H02M7/217 , H02M7/219 , H03K17/687
Abstract: A wireless power receiver includes a rectifier with first and second inputs coupled to first and second terminals of a receiver coil, and having a first output coupled to ground and a second output at which a rectified voltage is produced. A first switch is coupled between the second input and ground, and is controlled by a first gate voltage generated at a first node. A second switch is coupled between the first node and ground, and is controlled by a second gate voltage. The first gate voltage closes the first switch to couple the second input to ground when the rectified voltage is less than a threshold voltage, boosting the rectified voltage. The second gate voltage closes the second switch to cause the second gate voltage to be pulled to ground when the rectified voltage is greater than the threshold voltage, limiting the boosting of the rectified voltage.
-
公开(公告)号：US12142938B2
公开(公告)日：2024-11-12
申请号：US18412718
申请日：2024-01-15
Applicant: STMicroelectronics Asia Pacific Pte Ltd.
Inventor： Yannick Guedon
Abstract: An over-voltage protection circuit and methods of operation are provided. In one embodiment, a method includes monitoring a voltage at an output of a rectifier, a voltage at an output of a voltage regulator, or a combination thereof. The method further includes determining the over-voltage condition based on the monitoring; and in response to determining the over-voltage condition, regulating the voltage at the output of the rectifier in accordance with a voltage difference between the voltage at the output of the rectifier and the voltage at the output of the voltage regulator.
-
Patent Agency Ranking
公开(公告)号：US12040724B2
公开(公告)日：2024-07-16
申请号：US17576120
申请日：2022-01-14
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Yannick Guedon
Abstract: A bridge rectifier and associated control circuitry collectively form a “regtifier” which rectifies an input time varying voltage and regulates the rectified output voltage produced without the use of a traditional voltage regulator. To accomplish this, the gate voltages of transistors of the bridge rectifier that are on during a given phase may be modulated via analog control (to increase the on-resistance of those transistors) or via pulse width modulation (to turn off those transistors prior to the end of the phase). The transistors of the bridge rectifier that would otherwise be off during a given phase may be turned on to help dissipate excess power and thereby regulate the output voltage. This modulation is based upon both a voltage feedback signal and a current feedback signal.
-
257.发明公开公开(公告)号：US20240106344A1
公开(公告)日：2024-03-28
申请号：US18523488
申请日：2023-11-29
Applicant: STMicroelectronics Asia Pacific Pte Ltd
Inventor： Thanh HA TIEN , Yannick GUEDON
IPC: H02M7/219 , G01R19/165 , H02J50/12 , H02M1/00 , H02M1/32
CPC classification number: H02M7/219 , G01R19/16571 , H02J50/12 , H02M1/0009 , H02M1/32
Abstract: A wireless power-reception system has a bridge rectifier with two high-side and two low-side transistors, linked to input-nodes and sense-resistors. During a first phase, a control circuit activates certain transistors for rectification, producing an output voltage, while modulating a gate voltage of a non-activated low-side transistor to dissipate excess power and regulate the output voltage. During a first given number of occurrences of the first phase, the control circuit determines the current through the low-side transistor having its gate voltage modulated based upon a voltage across a first sense resistor coupled between that low-side transistor and ground. During a second given number of occurrences of the first phase, the control circuit determines the current delivered to the load based upon a voltage across the first sense resistor and a voltage across a second sense resistor coupled between the other low-side transistor and ground.
-
公开(公告)号：US20240088711A1
公开(公告)日：2024-03-14
申请号：US17941199
申请日：2022-09-09
Inventor： Baranidharan Karuppusamy , Abhay Jaisen Bhanushali
CPC classification number: H02J50/10 , H02J7/00711 , H02J7/00712 , H02J50/80 , H02J2207/20
Abstract: A method for operating a wireless power transmitter includes: receiving a power control command from a wireless power receiver; computing a potential voltage change for a transmitter voltage of the wireless power transmitter in accordance with a target transmitter power and a present value of a transmitter current of the wireless power transmitter; comparing the potential voltage change with a discrete step size of a supply voltage; and in response to determining that the magnitude of the potential voltage change is equal to or larger than the discrete step size of the supply voltage, adjusting the transmitter power by: adjusting the supply voltage by one or more discrete steps; and controlling a power conversion circuit of the wireless power transmitter using a target current value computed in accordance with the target transmitter power and the adjusted supply voltage.
-
公开(公告)号：US11836318B1
公开(公告)日：2023-12-05
申请号：US17901067
申请日：2022-09-01
Applicant: STMicroelectronics Asia Pacific Pte Ltd.
Inventor： Tchung Jing Siaw , Chen Khoi Chin , Jenn Woei Soo , Cheng Hung Lin
CPC classification number: G06F3/04184 , G06F3/0441 , G06F3/0442 , G06F3/0446 , G09G3/2096 , G09G2320/0247
Abstract: A method for operating an electronic device includes a touchscreen controller determining based on a frequency of a vertical synchronization signal (Vsync), whether a first display frame includes an idle time, the idle time being a duration of time remaining in the first display frame after an image displayed on a display of the electronic device is updated during the first display frame. The method further includes in response to determining that the first display frame includes the idle time, the touchscreen controller transmitting an uplink signal in the first display frame, the uplink signal being transmitted during the idle time of the first display frame.
-
公开(公告)号：US11765006B2
公开(公告)日：2023-09-19
申请号：US17245890
申请日：2021-04-30
Applicant: STMicroelectronics Asia Pacific Pte Ltd.
Inventor： Ade Putra , Kusuma Adi Ningrat , Mythreyi Nagarajan
CPC classification number: H04L27/22 , G06F3/04162 , G06F3/04166 , H03M1/124
Abstract: A device includes an analog to digital converter configured to convert voltages into a digital signal by sampling the voltages at a fixed sampling time; a first multiplier configured to multiply the digital signal with in-phase coefficients, the in-phase coefficients generated to produce a demodulated in-phase signal at a demodulation signal frequency; a first adder configured accumulate the demodulated in-phase signal to output in-phase magnitude values; a second multiplier configured to multiply the digital signal with quadrature coefficients, the quadrature coefficients generated to produce a demodulated quadrature signal at the demodulation signal frequency; and a second adder configured to accumulate the demodulated quadrature signal to output quadrature magnitude values.
-
-
-
-
-
-
-
-
-
Search Results
426
records
(took 0.03 seconds)
