公开(公告)号：US20040264580A1

公开(公告)日：2004-12-30

申请号：US10801983

申请日：2004-03-16

Applicant: STMicroelectronics Asia Pacific Pte Ltd.

Inventor： Patricia Chiang Wei Yin ,  Lucas Y.W. Hui ,  Jean-Michel Bard

IPC: H04N007/12

CPC classification number: H04N19/198 ,  H04N19/115 ,  H04N19/124 ,  H04N19/137 ,  H04N19/14 ,  H04N19/149 ,  H04N19/152 ,  H04N19/157 ,  H04N19/172 ,  H04N19/174 ,  H04N19/176 ,  H04N19/196 ,  H04N19/40 ,  H04N19/427 ,  H04N19/428 ,  H04N19/577 ,  H04N19/61 ,  H04N19/90

Abstract: A method of processing video frame data includes the steps of: receiving a video frame; partially decoding the video frame; fully decoding the video frame to produce macroblocks; determining video data parameters from the partially decoded video frame or both the partially and fully decoded video frame; and encoding the macroblocks based on the determined video data parameters to provide a compressed video frame for subsequent display.

Abstract translation: 一种处理视频帧数据的方法包括以下步骤：接收视频帧; 部分解码视频帧; 完全解码视频帧以产生宏块; 从部分解码的视频帧或部分和完全解码的视频帧中确定视频数据参数; 以及基于所确定的视频数据参数对所述宏块进行编码，以提供用于后续显示的压缩视频帧。

公开(公告)号：US20040141554A1

公开(公告)日：2004-07-22

申请号：US10677629

申请日：2003-10-02

Applicant: STMicroelectronics Asia Pacific Pte Ltd

Inventor： Kah-Ho Phong ,  Lucas Y.W. Hui

IPC: H04N007/12

CPC classification number: G06T1/60 ,  H04N19/433

Abstract: A cache memory system for use in a motion estimation system is disclosed. The system includes: a first cache memory defined in terms of a first width and a first height, and a second cache memory defined in terms of a second width and a second height, wherein said second height is less than said first height, the cache memory system being operable in one of two modes: the first mode being characterized by banks of memory from the second cache memory being concatenated vertically such that their concatenated height is at least equal to the first height, and said concatenated banks being arranged to be appended to the width of the first cache memory to form a single contiguous address space; and the second mode being characterized by banks of memory from the first and second cache being stacked vertically, and being arranged to be addressed as two separate address spaces.

Abstract translation: 公开了一种用于运动估计系统的高速缓冲存储器系统。 该系统包括：根据第一宽度和第一高度定义的第一高速缓存存储器和根据第二宽度和第二高度定义的第二高速缓存存储器，其中所述第二高度小于所述第一高度，高速缓存 存储器系统可以以两种模式之一操作：第一模式的特征在于来自第二高速缓冲存储器的存储器组被垂直级联，使得它们的级联高度至少等于第一高度，并且所述级联存储体被布置为被附加 到第一个高速缓冲存储器的宽度以形成单个连续的地址空间; 并且第二模式的特征在于来自第一和第二高速缓存的存储器组是垂直堆叠的，并且被布置为被寻址为两个单独的地址空间。

公开(公告)号：US20030169371A1

公开(公告)日：2003-09-11

申请号：US10356719

申请日：2003-01-30

Applicant: STMicroelectronics Asia Pacific Pte. Ltd.

Inventor： Patricia Wei Yin Chiang ,  Lucas Y.W. Hui

IPC: H04N009/455

CPC classification number: H04N19/423 ,  H04N19/61

Abstract: A method of transferring sets of video line data and macroblock data, comprising the steps of determining a macroblock period and a video line period longer than the macroblock period, dividing each set of video line data to be transferred within the video line period into two or more portions according to the difference between the determined macroblock period and video line period, aligning a burst transfer of each of the portions of the divided set of video line data and each set of macroblock data to the macroblock period, and initiating the burst transfer of the sets of video line data and macroblock data at macroblock period intervals.

Abstract translation: 一种传输视频行数据和宏块数据集的方法，包括以下步骤：确定比宏块周期长的宏块周期和视频行周期，将在视频行周期内传送的每组视频行数据划分成两个或 根据所确定的宏块周期和视频行周期之间的差异来更多部分，将分割的视频行数据集合的每个部分的突发传送与每个宏块数据集对齐到宏块周期，并且发起突发传送 在宏块周期间隔的视频行数据和宏块数据集合。