公开(公告)号：US20120113695A1

公开(公告)日：2012-05-10

申请号：US13291589

申请日：2011-11-08

Applicant: Francisco Javier CHIVITE ZABALZA ,  Miguel Angel RODRIGUEZ VIDAL ,  Danel MADARIAGA ZUBIMENDI ,  Pedro IZURZA MORENO ,  Gorka CALVO OLALLA

Inventor： Francisco Javier CHIVITE ZABALZA ,  Miguel Angel RODRIGUEZ VIDAL ,  Danel MADARIAGA ZUBIMENDI ,  Pedro IZURZA MORENO ,  Gorka CALVO OLALLA

IPC: H02M7/44

CPC classification number: H02M7/49 ,  H02M7/487 ,  H02M2001/009

Abstract: A control method and apparatus are provided to convert a DC voltage into alternating voltage. The apparatus includes a first inverter and a second inverter to generate a first alternating voltage and a second alternating voltage, respectively. Also included is an interphase transformer to combine these alternating voltages in parallel to obtain a first resulting alternating voltage. The apparatus also includes a third inverter and a fourth inverter to generate a third and fourth alternating voltage, respectively. These are combined to form a second resulting alternating voltage. The second resulting alternating voltage is displaced in phase approximately 180° in relation to the first resulting alternating voltage.

Abstract translation: 提供一种将DC电压转换为交流电压的控制方法和装置。 该装置包括分别产生第一交流电压和第二交流电压的第一逆变器和第二逆变器。 还包括一个并联的这些交流电压的相间变压器，以获得第一个产生的交流电压。 该装置还包括分别产生第三和第四交流电压的第三反相器和第四反相器。 这些被组合以形成第二个产生的交流电压。 第二个产生的交流电压相对于第一个产生的交流电压相位大约180°。

公开(公告)号：US20100173244A1

公开(公告)日：2010-07-08

申请号：US12665971

申请日：2008-06-20

Applicant: Daniel Patrick Morris ,  John Dylan Morgan ,  Martin Russell Edwards ,  Miguel Angel Rodriguez-Vazquez ,  Mohammed Nawaz ,  Zoonia Mehmood

Inventor： Daniel Patrick Morris ,  John Dylan Morgan ,  Martin Russell Edwards ,  Miguel Angel Rodriguez-Vazquez ,  Mohammed Nawaz ,  Zoonia Mehmood

IPC: G03G9/087 ,  G03G9/09

CPC classification number: G03G9/0804 ,  G03G9/0819 ,  G03G9/0827 ,  G03G9/08755 ,  G03G9/08795

Abstract: A process for preparing a toner comprising a binder resin and a colorant, wherein the binder resin comprises a polyester resin having an acid value greater than 5 mg KOH/g, the process comprising: providing an aqueous dispersion of polyester resin particles stabilised by an ionic surfactant and then associating the polyester resin particles.

Abstract translation: 一种用于制备包含粘合剂树脂和着色剂的调色剂的方法，其中所述粘合剂树脂包含酸值大于5mg KOH / g的聚酯树脂，所述方法包括：提供由离子稳定的聚酯树脂颗粒的水分散体 然后使聚酯树脂颗粒缔合。

公开(公告)号：US12145555B2

公开(公告)日：2024-11-19

申请号：US16974125

申请日：2020-10-14

Applicant: Angel Rodriguez-Cruz

Inventor： Angel Rodriguez-Cruz

IPC: B60T3/00 ,  B60P3/077 ,  B66F3/08

Abstract: PROPCA is a multi-purpose tool composed of two chocks joined by groove and protrusion. Installing the handle (bolt and spike) through the bottom of PROPCA could be used to remove dirt or snow, separate, each can perform various tasks due to particular form and drill holes in specific areas. The reduction in size allows the creation of different and more manageable tools, with better efficiency helping each other in the accomplishment of different task. To separate PROPCA, the spike and bolt should be removed and both chocks slide apart. That single chock could be used as a jack, hammer, nail remover, scraper, pickaxe, or as a tire catapult or tire restrainer. Both chocks could work together to remove the rim from the flat tire. Ordinary vehicle tools are limited in performance. A multi-purpose tools could be the difference when physical integrity is at risk.

公开(公告)号：US20190254917A1

公开(公告)日：2019-08-22

申请号：US15932342

申请日：2018-02-20

Applicant: Angel Rodriguez-Cruz

Inventor： Angel Rodriguez-Cruz

IPC: A61H3/04 ,  A61G5/10 ,  A61G5/12 ,  A61H3/02

Abstract: Wheeleta comprises a regular wheelchair to which, the front area has been altered to adapt a pair of crutches. Wheeleta crutch assembly includes the wedges, the sheath, the spear and the handle with under arm cushion area and the bar. It will attach the handle to the spear by lifting the button and introducing the bar into the spear until the previously established height is reached. The button is liberated and the height is fixed. The wedge is attached to the end of the spear and kept in place by a pivot with an open end with a rotating metal blade. The crutches could be out of way by twisting the spear in its own sheath and utilized by the user when rises to go out or entering the chair. The crutches could be removed from the sheath by lifting and pushing the crutch. The wedges also, could be completely removed from the spear by twisting the flip at the end of the crutch pivot. The crutch handle with bar could be removed out of the spear and used to reach objects.

公开(公告)号：US20170048470A1

公开(公告)日：2017-02-16

申请号：US15220473

申请日：2016-07-27

Applicant: Jorge Fernandez-Berni ,  Michael Neimier ,  Xiabobo Sharon Hu ,  Ricardo Carmona-Galan ,  Angel Rodriguez-Vasquez

Inventor： Jorge Fernandez-Berni ,  Michael Niemier ,  Xiabobo Sharon Hu ,  Ricardo Carmona-Galan ,  Angel Rodriguez-Vazquez

IPC: H04N5/355 ,  H01L27/146 ,  H04N5/353 ,  H04N5/374 ,  H04N5/378

CPC classification number: H01L27/14612 ,  H01L27/14643 ,  H04N5/35581 ,  H04N5/374

Abstract: Embodiments of the disclosure provide a solution to carry out High Dynamic Range (HDR) imaging based on dynamic well capacity adjustment without incurring additional spatial-temporal noise and consequent Signal-to-Noise Ratio (SNR) dips caused by the sub-threshold operation of a CMOS (Complementary Metal-Oxide-Semiconductor) reset transistor in a pixel cell. Embodiments of the disclosure employ realizations of transistors other than CMOS, e.g. Tunnel Field-Effect Transistors (TFETs), featuring asymmetric conduction between two of its terminals, where asymmetric conduction means that current can only flow in one direction between those two terminals. In some embodiments, one of such realizations plays the role of the pixel reset transistor in order to exploit the asymmetric conduction to perform dynamic well capacity adjustment. As a result, the sources of spatial-temporal noise arising from the sub-threshold operation of the pixel reset transistor in CMOS implementations are removed.

Abstract translation: 本公开的实施例提供了一种基于动态井容量调整来执行高动态范围（HDR）成像的解决方案，而不会引起额外的空间 - 时间噪声以及由次阈值操作引起的随后的信噪比（SNR）下降 像素单元中的CMOS（互补金属氧化物半导体）复位晶体管。 本公开的实施例采用除CMOS之外的晶体管的实现，例如， 隧道场效应晶体管（TFET），其两个端子之间具有不对称导通，其中不对称传导意味着电流只能在这两个端子之间沿一个方向流动。 在一些实施例中，这种实现之一起到像素复位晶体管的作用，以利用非对称导通来执行动态阱容量调整。 结果，去除了CMOS实现中的像素复位晶体管的子阈值操作产生的空间 - 时间噪声源。

公开(公告)号：US20130236048A1

公开(公告)日：2013-09-12

申请号：US13417279

申请日：2012-03-11

Applicant: Angel Rodriguez Vazquez ,  Fernando Rafael Pardo Seco ,  Manuel Suarez Cambre ,  Ricardo Carmona Galan ,  Victor Manuel Brea Sanchez

Inventor： Angel Rodriguez Vazquez ,  Fernando Rafael Pardo Seco ,  Manuel Suarez Cambre ,  Ricardo Carmona Galan ,  Victor Manuel Brea Sanchez

IPC: G06K9/46

CPC classification number: G06K9/00986 ,  G06K9/4671

Abstract: Disclose embodiments include an image processor for feature detection comprising a single non-planar chip containing a plurality of integrated sensing and processing resources across two or more layers adapted to capture image frames and extract image features. In a particular embodiment, the non-planar chip is a three dimensional CMOS integrated circuit (3D CMOS IC) with vertical distribution of sensing and processing resources across two or more vertical integrated circuit layers. The 3D CMOS IC implements two or more feature detectors in a single chip by reusing a plurality of circuits employed for gradient and keypoint detection. Feature detectors include a scale invariant feature transform detector (SIFT), a Harris-based feature detector, and a Hessian-based feature detector.

Abstract translation: 揭示实施例包括用于特征检测的图像处理器，其包括跨越适于捕获图像帧并提取图像特征的跨越两个或更多个层的多个集成感测和处理资源的单个非平面芯片。 在特定实施例中，非平面芯片是三维CMOS集成电路（3D CMOS IC），其具有横跨两个或多个垂直集成电路层的感测和处理资源的垂直分布。 3D CMOS IC通过重复使用用于梯度和关键点检测的多个电路，在单个芯片中实现两个或更多个特征检测器。 特征检测器包括尺度不变特征变换检测器（SIFT），基于哈里斯的特征检测器和基于Hessian的特征检测器。

公开(公告)号：US07515550B2

公开(公告)日：2009-04-07

申请号：US11504491

申请日：2006-08-15

Applicant: Kenneth D. Franklin ,  Robert J. Bates ,  Frederick Edwards ,  Noland Smith ,  Klaudio Kucelin ,  Joel E. Cordsmeyer ,  Noris C. Tsangarides ,  Angel Rodriguez ,  Steven Dominie ,  Jean-Pierre Zaiter ,  Zhao Ming Li ,  Michael Hebert

Inventor： Kenneth D. Franklin ,  Robert J. Bates ,  Frederick Edwards ,  Noland Smith ,  Klaudio Kucelin ,  Joel E. Cordsmeyer ,  Noris C. Tsangarides ,  Angel Rodriguez ,  Steven Dominie ,  Jean-Pierre Zaiter ,  Zhao Ming Li ,  Michael Hebert

IPC: H04L12/26

CPC classification number: H04L43/0852 ,  H04L41/0213 ,  H04L41/0233 ,  H04L41/0806 ,  H04L41/5054

Abstract: A system for automatically monitoring provisioning in a DSL network is disclosed. The system is operable to query network elements in the DSL network for information related to the provisioning of DSL services. Thereafter, the system analyzes the information to identify points of delay and/or failure in the provisioning process. If a delay exceeds a threshold value, an administrator is notified.

Abstract translation: 公开了一种用于自动监视DSL网络中的配置的系统。 该系统可操作地查询DSL网络中的网元，以获得与DSL服务的提供有关的信息。 此后，系统分析信息以识别供应过程中的延迟点和/或故障点。 如果延迟超过阈值，则通知管理员。

公开(公告)号：US20070136265A1

公开(公告)日：2007-06-14

申请号：US11301901

申请日：2005-12-13

Applicant: Rashmi Hunt ,  Zeenat Kulkarni ,  Jose Angel Rodriguez ,  Edwin Sapugay ,  Olga Tikhonova ,  Hai Zhao

Inventor： Rashmi Hunt ,  Zeenat Kulkarni ,  Jose Angel Rodriguez ,  Edwin Sapugay ,  Olga Tikhonova ,  Hai Zhao

IPC: G06F17/30

CPC classification number: G06F17/30604 ,  G06Q40/00

Abstract: An apparatus, system, and method are disclosed for automatically maintaining identity relationships among disparate enterprise information systems. The apparatus comprises a synchronization hub comprising an identity relationship repository, a relationship service module, a consistency module, and an adjustment module. The relationship service is configured to access a target relationship entry using a unique key from a source business object, wherein the source business object is representative of changes made in a source enterprise information system. The various components and modules of the synchronization hub cooperate to determine identity relationships that need updating and to propagate identity relationship changes to one or more destination enterprise information servers.

Abstract translation: 公开了用于自动维护不同企业信息系统之间的身份关系的装置，系统和方法。 该装置包括同步集线器，其包括身份关系库，关系服务模块，一致性模块和调整模块。 关系服务被配置为使用来自源业务对象的唯一密钥来访问目标关系条目，其中源业务对象代表源企业信息系统中所做的更改。 同步中心的各种组件和模块合作确定需要更新的身份关系，并将身份关系更改传播到一个或多个目标企业信息服务器。

公开(公告)号：US5185799A

公开(公告)日：1993-02-09

申请号：US835639

申请日：1992-02-13

Applicant: John McNesby ,  Amritpal S. Kalla ,  Angel Rodriguez

Inventor： John McNesby ,  Amritpal S. Kalla ,  Angel Rodriguez

IPC: H04L25/03 ,  H04L25/48

CPC classification number: H04L25/03872

Abstract: A data scrambler circuit which adds the SONET polynomial 1+X.sup.6 +X.sup.7 to data in a parallel format to thereby reduce circuitry clock rates to one-eighth the line rate, which reduces power consumption and simplifies timing constraints. A circuit embodiment includes a first series of flip-flops connected to generate the polynomial and a second series of flip-flops for holding the generated polynomial. To provide a relatively large window of time for looking at the data, parallel data is obtained by providing a parallel-to-parallel register at the output of a serial-to-parallel register. The parallel data is added to the held polynomial by a series of exclusive OR gates.

Abstract translation: 一种数据加扰电路，其以并行格式将SONET多项式1 + X6 + X7添加到数据，从而将电路时钟速率降低到线路速率的八分之一，这降低了功耗并简化了时序约束。 电路实施例包括连接以产生多项式的第一系列触发器和用于保持所生成的多项式的第二系列触发器。 为了提供用于查看数据的相当大的时间窗口，通过在串行到并行寄存器的输出端提供并行到并行寄存器来获得并行数据。 并行数据通过一系列异或门加到保持多项式中。

公开(公告)号：US5163092A

公开(公告)日：1992-11-10

申请号：US619155

申请日：1990-11-28

Applicant: John McNesby ,  Amritpal S. Kalla ,  Angel Rodriguez

Inventor： John McNesby ,  Amritpal S. Kalla ,  Angel Rodriguez

IPC: H04L9/18 ,  H04L25/03

CPC classification number: H04L25/03872

Abstract: A data scrambler circuit which adds the SONET polynomial 1+X.sup.6 +X.sup.7 to data in a parallel format to thereby reduce circuitry clock rates to one-eighth the line rate, which reduces power consumption and simplifies timing constraints. A circuit embodiment includes a first series of flip-flops connected to generate the polynomial and a second series of flip-flops for holding the generated polynomial. The parallel data is added to the held polynomial by a series of exclusive OR gates.