Abstract:
According to an embodiment of the invention, a method and apparatus are described for memory trace buffering. An embodiment of a processor includes an execution unit and a buffer. The buffer is to store certain data regarding each memory operation of a plurality of memory operations that are executed by the processor.
Abstract:
A method for concurrent management of adaptive programs is disclosed wherein changes in a set of modifiable references are initially identified. A list of uses of the changed references is next computed using records made in structures of the references. The list is next inserted into an elimination queue. Comparison is next made of each of the uses to the other uses to determine independence or dependence thereon. Determined dependent uses are eliminated and the preceding steps are repeated for all determined independent uses until all dependencies have been eliminated.
Abstract:
A method for evaluating objects in a data structure is provided. The method comprises assigning one or more objects to one or more nodes in a data structure having at least a root node, wherein the objects are assigned to the nodes in accordance with a first order to maintain pre-existing dependencies between said objects and to allow the objects to be evaluated in a serial manner to avoid deadlock when concurrently executing threads to evaluate the objects; and selecting a first object for evaluation, in response to determining that the current object is unevaluated.
Abstract:
In one embodiment, the present invention includes a cache memory having a plurality of cache lines to store data, in which at least some of the cache lines are adapted to store data in a compressed state. The cache memory also may include a first tag corresponding to each of the cache lines to indicate whether data in the corresponding cache line is compressible.
Abstract:
In one embodiment, the invention provides a method comprising determining metadata encoded in instructions of a stored program; and executing the stored program based on the metadata.
Abstract:
A memory controller is described that comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information. A processor and a memory controller integrated on a same semiconductor die is also described. The memory controller comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information.