Future scheduling by direct representation of possible dependencies
    3.
    发明授权
    Future scheduling by direct representation of possible dependencies 有权
    通过直接表示可能依赖的未来调度

    公开(公告)号:US08225326B2

    公开(公告)日:2012-07-17

    申请号:US12049914

    申请日:2008-03-17

    CPC classification number: G06F9/524

    Abstract: A method for evaluating objects in a data structure is provided. The method includes assigning one or more objects to one or more nodes in a data structure having at least a root node, in which the objects are assigned to the nodes in accordance with a first order to maintain pre-existing dependencies between the objects and to allow the objects to be evaluated in a serial manner to avoid deadlock when concurrently executing threads to evaluate the objects, and selecting a first object for evaluation, in response to determining that the current object is unevaluated.

    Abstract translation: 提供了一种用于评估数据结构中的对象的方法。 该方法包括将一个或多个对象分配给具有至少根节点的数据结构中的一个或多个节点,其中根据第一顺序将对象分配给节点,以保持对象之间的预先存在的依赖关系,以及 允许以串行方式评估对象,以在同时执行线程以评估对象时选择第一对象以进行评估,以响应于确定当前对象未被评估而避免死锁。

    Compression-decompression mechanism
    6.
    发明申请
    Compression-decompression mechanism 审中-公开
    压缩减压机理

    公开(公告)号:US20050071151A1

    公开(公告)日:2005-03-31

    申请号:US10676430

    申请日:2003-09-30

    CPC classification number: H03M7/30

    Abstract: According to one embodiment a method is disclosed. The method includes receiving a string of data symbols, and compressing the string of symbols into a compressed data block having a plurality of compressed symbols and dictionary elements. The compressed data block has a fixed offset and the symbols and dictionary elements have a fixed length.

    Abstract translation: 根据一个实施例,公开了一种方法。 该方法包括接收一串数据符号,并将该符号串压缩成具有多个压缩符号和字典元素的压缩数据块。 压缩数据块具有固定的偏移量,符号和字典元素具有固定的长度。

    Inserting prefetch instructions based on hardware monitoring
    7.
    发明申请
    Inserting prefetch instructions based on hardware monitoring 审中-公开
    根据硬件监控插入预取指令

    公开(公告)号:US20070150660A1

    公开(公告)日:2007-06-28

    申请号:US11320201

    申请日:2005-12-28

    CPC classification number: G06F12/0862

    Abstract: A compiler or runt-time system may determine a prefetch point to insert an instruction in order to prefetch a memory location and thereby reduce latency in accessing information from a cache. A prefetch predictor generator may decide where and whether to insert the appropriate instructions by looking at information from a hardware monitor. For example, information about cache misses may be analyzed. The differences between target addresses of those cache misses for different instructions may be determined. This information may also be used to determine the locations in the program where the prefetch instructions should be placed, as well as to calculate the address of the memory location being prefetched.

    Abstract translation: 编译器或runt-time系统可以确定预取点来插入指令以便预取存储器位置,从而减少从高速缓存访​​问信息的延迟。 预取预测器发生器可以通过查看来自硬件监视器的信息来决定何处以及是否插入适当的指令。 例如,可以分析关于高速缓存未命中的信息。 可以确定不同指令的那些高速缓存未命中的目标地址之间的差异。 该信息还可以用于确定应该放置预取指令的程序中的位置,以及计算正在预取的存储器位置的地址。

    Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system
    9.
    发明申请
    Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system 失效
    多处理器计算系统采用压缩缓存行的信息和能够在所述系统中使用的处理器

    公开(公告)号:US20050160234A1

    公开(公告)日:2005-07-21

    申请号:US10759922

    申请日:2004-01-15

    CPC classification number: G06F12/0886 G06F12/0802 G06F12/0864 G06F2212/401

    Abstract: Cache coherency rules for a multi-processor computing system that is capable of working with compressed cache lines' worth of information are described. A multi-processor computing system that is capable of working with compressed cache lines' worth of information is also described. The multi-processor computing system includes a plurality of hubs for communicating with various computing system components and for compressing/decompressing cache lines' worth of information. A processor that is capable of labeling cache lines' worth of information in accordance with the cache coherency rules is described. A processor that includes a hub as described above is also described.

    Abstract translation: 描述了能够处理压缩高速缓存行的信息量的多处理器计算系统的缓存一致性规则。 还描述了能够处理压缩高速缓存行的信息的多处理器计算系统。 多处理器计算系统包括用于与各种计算系统组件进行通信并用于压缩/解压缩高速缓存行的信息价值的多个集线器。 描述了能够根据高速缓存一致性规则来标记高速缓存线值的信息的处理器。 还描述了包括如上所述的集线器的处理器。

    Mechanism to improve performance monitoring overhead
    10.
    发明申请
    Mechanism to improve performance monitoring overhead 审中-公开
    提高绩效监测开销的机制

    公开(公告)号:US20050146449A1

    公开(公告)日:2005-07-07

    申请号:US10748875

    申请日:2003-12-30

    CPC classification number: H03M7/30

    Abstract: In one embodiment, a method is provided. The method of this embodiment provides reading one or more records event data, the one or more event data corresponding to an event monitored from a system; for each event datum, compressing the event datum if the event datum is determined to be compressible; creating a processed event record, the processed event record conforming to a record format; and storing the one or more event data in the processed event record in accordance with the record format.

    Abstract translation: 在一个实施例中,提供了一种方法。 该实施例的方法提供读取一个或多个记录事件数据,所述一个或多个事件数据对应于从系统监视的事件; 对于每个事件数据,如果事件数据被确定为可压缩的则压缩事件数据; 创建处理的事件记录,符合记录格式的已处理事件记录; 以及根据记录格式将所述一个或多个事件数据存储在所处理的事件记录中。

Patent Agency Ranking