公开(公告)号：US20120092944A1

公开(公告)日：2012-04-19

申请号：US12968582

申请日：2010-12-15

Applicant: Tzu-Kuei LIN ,  Hung-Jen LIAO ,  Shao-Yu CHOU ,  Ching-Wei WU

Inventor： Tzu-Kuei LIN ,  Hung-Jen LIAO ,  Shao-Yu CHOU ,  Ching-Wei WU

IPC: G11C7/22

CPC classification number: G11C7/222

Abstract: A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.

Abstract translation: 存储器件具有存储器组件和时钟偏斜发生器，支持在存储器件的读取，读写和写入 - 写入操作模式中可能巧合地发生的至少两个读和写操作。 时钟偏移发生器产生至少两个稳定和平衡的时钟通道，其承载至少两个时钟信号，并且改变时钟信号边沿的相对定时，从而在这些操作模式中随时移动边缘，其中同时的边缘将导致有害的 加载。

公开(公告)号：US07613054B2

公开(公告)日：2009-11-03

申请号：US11924437

申请日：2007-10-25

Applicant: Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

Inventor： Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

IPC: G11C7/00

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

Abstract translation: SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线 局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

公开(公告)号：US08845247B2

公开(公告)日：2014-09-30

申请号：US13170793

申请日：2011-06-28

Applicant: Ching-Wei Wu ,  Ying-Shing Shiao ,  Chia-Hui Tang ,  Yu-Che Wang ,  Paul Chang

Inventor： Ching-Wei Wu ,  Ying-Shing Shiao ,  Chia-Hui Tang ,  Yu-Che Wang ,  Paul Chang

IPC: B23Q15/18

CPC classification number: B23Q15/18 ,  G05B2219/45145 ,  G05B2219/49207 ,  G05B2219/49219 ,  Y10T409/300896 ,  Y10T409/306832 ,  Y10T409/307224 ,  Y10T409/309744

Abstract: A milling machine has a base, a work platform mounted movably on the base, and a ruler mounted on the work platform. The work platform is movable relative to a base axis. The thermal compensation system includes a sensor and a control unit. The sensor is configured to be mounted on the base for sensing a position of each of the work platform and the ruler relative to the base axis. The control unit is coupled to the sensor, and determines a work platform displacement and a ruler displacement according to the positions sensed by the sensor. The control unit further calculates a compensation value based on the work platform displacement and the ruler displacement. The control unit is configured to correct the position of the work platform relative to the base axis according to the compensation value.

Abstract translation: 铣床具有基座，可移动地安装在基座上的工作平台和安装在工作平台上的标尺。 工作平台相对于基础轴线是可移动的。 热补偿系统包括传感器和控制单元。 传感器被配置为安装在基座上，用于感测工作平台和标尺中的每一个相对于基轴的位置。 控制单元耦合到传感器，并根据传感器感测到的位置确定工作平台位移和尺子位移。 控制单元进一步基于工作平台位移和标尺位移来计算补偿值。 控制单元被配置为根据补偿值来校正工作平台相对于基准轴的位置。

公开(公告)号：US08488395B2

公开(公告)日：2013-07-16

申请号：US12754733

申请日：2010-04-06

Applicant: Cheng Hung Lee ,  Ching-Wei Wu ,  Bin Sheng ,  Hung-Jen Liao

Inventor： Cheng Hung Lee ,  Ching-Wei Wu ,  Bin Sheng ,  Hung-Jen Liao

IPC: G11C7/00

CPC classification number: H01L27/1104 ,  G11C11/419

Abstract: A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter.

Abstract translation: 集成电路的保持器包括具有与反相器的输出端耦合的第一栅极的第一晶体管。 第二晶体管与第一晶体管串联耦合。 第二晶体管具有与反相器的输入端耦合的第二栅极。

公开(公告)号：US08395950B2

公开(公告)日：2013-03-12

申请号：US12968582

申请日：2010-12-15

Applicant: Tzu-Kuei Lin ,  Hung-Jen Liao ,  Shao-Yu Chou ,  Ching-Wei Wu

Inventor： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Shao-Yu Chou ,  Ching-Wei Wu

IPC: G11C7/00

CPC classification number: G11C7/222

Abstract: A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.

Abstract translation: 存储器件具有存储器组件和时钟偏斜发生器，支持在存储器件的读取，读写和写入 - 写入操作模式中可能巧合地发生的至少两个读和写操作。 时钟偏移发生器产生至少两个稳定和平衡的时钟通道，其承载至少两个时钟信号，并且改变时钟信号边沿的相对定时，从而在这些操作模式中随时移动边缘，其中同时的边缘将导致有害的 加载。

公开(公告)号：US20110019460A1

公开(公告)日：2011-01-27

申请号：US12784133

申请日：2010-05-20

Applicant: Ching-Wei Wu ,  Cheng Hung Lee ,  Li-Chen Chen ,  Weiyang Jiang

Inventor： Ching-Wei Wu ,  Cheng Hung Lee ,  Li-Chen Chen ,  Weiyang Jiang

IPC: G11C17/00 ,  H01L21/82

CPC classification number: G11C17/10 ,  H01L27/112

Abstract: A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines.

Abstract translation: 存储电路包括多个位线。 第一存储单元和第二存储单元串联耦合。 第一存储单元和第二存储单元中的每一个能够存储第一类型的数据。 第一存储单元和第二存储单元共享第一公共源极/漏极（S / D）区域。 第一公共S / D区域与所有位线电隔离。

公开(公告)号：US20090109768A1

公开(公告)日：2009-04-30

申请号：US11924437

申请日：2007-10-25

Applicant: Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

Inventor： Cheng-Hung Lee ,  Ping-Wei Wang ,  Ching-Wei Wu ,  Shu-Hsuan Lin ,  Feng-Ming Chang ,  Hung-Jen Liao

IPC: G11C7/00

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

Abstract translation: SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线 局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

公开(公告)号：US20060256635A1

公开(公告)日：2006-11-16

申请号：US11128846

申请日：2005-05-13

Applicant: Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

Inventor： Cheng-Hung Lee ,  Ching-Wei Wu ,  Hung-Jen Liao

IPC: G11C7/00

CPC classification number: G11C17/12 ,  G11C7/12 ,  G11C17/18

Abstract: A memory access method and a memory system are disclosed for shortening a memory cell access time. The memory system comprises one or more memory cells, at least one bit-line discharge subsystem having one or more discharge modules, each discharge module coupled to a bit-line connecting to one or more memory cells for discharging a voltage level of the bit-line upon a triggering of a discharge control signal, at least one sense amplifier coupled to the bit-line for determining data stored in a selected memory cell, at least one latch module for storing the determined data from the sense amplifier upon a triggering of a latch enable signal, wherein the discharge control signal is triggered prior to the triggering of the latch enable signal so that the voltage level of the bit-line is discharged for allowing an accelerated reading of the data.

Abstract translation: 公开了一种用于缩短存储器单元访问时间的存储器存取方法和存储器系统。 存储器系统包括一个或多个存储器单元，至少一个位线放电子系统，具有一个或多个放电模块，每个放电模块耦合到连接到一个或多个存储器单元的位线， 在触发放电控制信号时，连接到位线的至少一个读出放大器用于确定存储在所选择的存储器单元中的数据，至少一个锁存模块，用于在触发放大控制信号时从读出放大器存储所确定的数据 锁存使能信号，其中在触发锁存器使能信号之前触发放电控制信号，使得位线的电压电平被放电以允许数据的加速读取。