公开(公告)号：US08395950B2

公开(公告)日：2013-03-12

申请号：US12968582

申请日：2010-12-15

申请人： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Shao-Yu Chou ,  Ching-Wei Wu

发明人： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Shao-Yu Chou ,  Ching-Wei Wu

IPC分类号： G11C7/00

CPC分类号： G11C7/222

摘要： A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading.

摘要翻译： 存储器件具有存储器组件和时钟偏斜发生器，支持在存储器件的读取，读写和写入 - 写入操作模式中可能巧合地发生的至少两个读和写操作。 时钟偏移发生器产生至少两个稳定和平衡的时钟通道，其承载至少两个时钟信号，并且改变时钟信号边沿的相对定时，从而在这些操作模式中随时移动边缘，其中同时的边缘将导致有害的 加载。

公开(公告)号：US08077517B2

公开(公告)日：2011-12-13

申请号：US12338732

申请日：2008-12-18

申请人： Li-Wen Wang ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsien-Yu Pan ,  Shao-Yu Chou ,  Hung-Jen Liao

发明人： Li-Wen Wang ,  Yen-Huei Chen ,  Chen-Lin Yang ,  Hsien-Yu Pan ,  Shao-Yu Chou ,  Hung-Jen Liao

IPC分类号： G11C11/34

CPC分类号： G11C11/413 ,  G11C5/04 ,  G11C5/147

摘要： An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected.

摘要翻译： 集成电路结构包括存储器。 存储器包括与第一存储器宏相同的第一存储器宏和第二存储器宏。 第一功率块连接到第一存储器宏，并被配置为向第一存储器宏提供调节电压。 第一功率块具有第一输入和第一输出。 基本上与第一功率块相同的第二功率块连接到第二存储器宏，并且被配置为向第二存储器宏提供调节电压。 第二功率块具有第二输入和第二输出。 第一输入和第二输入互连。 第一个输出和第二个输出相互连接。

公开(公告)号：US20100124099A1

公开(公告)日：2010-05-20

申请号：US12273959

申请日：2008-11-19

申请人： Jui-Jen Wu ,  Yen-Huei Chen ,  Shao-Yu Chou ,  Hung-Jen Liao

发明人： Jui-Jen Wu ,  Yen-Huei Chen ,  Shao-Yu Chou ,  Hung-Jen Liao

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters having a storage node, and a NMOS transistor having a gate terminal, a first and a second source/drain terminal connected to the storage node, a read word-line (RWL) and a read bit-line (RBL), respectively, the RWL and RBL being activated during a read operation and not being activated during any write operation.

摘要翻译： 本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有存储节点的一对交叉耦合的反相器，以及具有栅极端子，连接到存储节点的第一和第二源极/漏极端子的NMOS晶体管， 分别读取字线（RWL）和读位线（RBL），RWL和RBL在读操作期间被激活，并且在任何写操作期间未被激活。

公开(公告)号：US08928113B2

公开(公告)日：2015-01-06

申请号：US13082497

申请日：2011-04-08

申请人： Hsien-Yu Pan ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Yen-Huei Chen ,  Hung-Jen Liao

发明人： Hsien-Yu Pan ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC分类号： H01L23/52 ,  H01L27/108 ,  H01L29/94 ,  H01L21/70 ,  H01L27/02 ,  H01L27/11 ,  H01L27/118

CPC分类号： H01L27/1116 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11 ,  H01L2027/11887

摘要： A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

摘要翻译： 用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。 晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

公开(公告)号：US20120313177A1

公开(公告)日：2012-12-13

申请号：US13158133

申请日：2011-06-10

申请人： Yen-Huei Chen ,  Wei Min Chan ,  Shao-Yu Chou ,  Hung-Jen Liao

发明人： Yen-Huei Chen ,  Wei Min Chan ,  Shao-Yu Chou ,  Hung-Jen Liao

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/0207 ,  H01L27/088 ,  H01L27/1104

摘要： A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions.

摘要翻译： 多指结构包括放置在一对虚拟POLY线之间的多个有源区域。 有源区域包括多个多指状NMOS晶体管，它们是SRAM存储器电路的读出放大器的一部分。 每个多指尖的NMOS晶体管的漏极和源极具有SiP / SiC外延生长区域。 有源区域与虚拟POLY线路延伸并重叠。 有源区域和虚拟POLY线之间的重叠有助于减少有源区域边缘处的边缘缺陷。

公开(公告)号：US07808812B2

公开(公告)日：2010-10-05

申请号：US12238850

申请日：2008-09-26

申请人： Jack Liu ,  Shao-Yu Chou ,  Hung-Jen Liao

发明人： Jack Liu ,  Shao-Yu Chou ,  Hung-Jen Liao

IPC分类号： G11C11/00

CPC分类号： G11C11/413

摘要： This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line.

摘要翻译： 本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有第一存储节点的一对交叉耦合的反相器，具有连接在第一存储节点和位线之间的源极和漏极的第一NMOS晶体管， 第二NMOS晶体管，其源极和漏极连接在第一NMOS晶体管的栅极和字线之间，第二NMOS晶体管具有连接到第一列选择线的栅极和具有源极和漏极的第三NMOS晶体管 连接在接地（VSS）和第一NMOS晶体管的栅极之间，以及连接到第二列选择线的栅极，第二列选择线与第一列选择线互补。

公开(公告)号：US20100080045A1

公开(公告)日：2010-04-01

申请号：US12238850

申请日：2008-09-26

申请人： Jack Liu ,  Shao-Yu Chou ,  Hung-Jen Liao

发明人： Jack Liu ,  Shao-Yu Chou ,  Hung-Jen Liao

IPC分类号： G11C11/00

CPC分类号： G11C11/413

摘要： This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line.

摘要翻译： 本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有第一存储节点的一对交叉耦合的反相器，具有连接在第一存储节点和位线之间的源极和漏极的第一NMOS晶体管， 第二NMOS晶体管，其源极和漏极连接在第一NMOS晶体管的栅极和字线之间，第二NMOS晶体管具有连接到第一列选择线的栅极和具有源极和漏极的第三NMOS晶体管 连接在接地（VSS）和第一NMOS晶体管的栅极之间，以及连接到第二列选择线的栅极，第二列选择线与第一列选择线互补。

公开(公告)号：US08767493B2

公开(公告)日：2014-07-01

申请号：US13169511

申请日：2011-06-27

申请人： Yen-Huei Chen ,  Kun-hsi Li ,  Shao-Yu Chou ,  Hung-Jen Liao ,  Wei Min Chan

发明人： Yen-Huei Chen ,  Kun-hsi Li ,  Shao-Yu Chou ,  Hung-Jen Liao ,  Wei Min Chan

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/062 ,  G11C11/419

摘要： An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier operates in a characterization mode, the transmission gates and pre-charge circuits are turned off. The differential voltage sensing apparatus applies a characterization signal to the sense amplifier and obtains the parameters of the memory circuit through a trial and error process.

摘要翻译： SRAM差分电压感测装置耦合到存储器电路。 存储器电路包括存储体，多个位线，经由多个传输门和读出放大器耦合到多个位线的多条数据线。 当感测放大器在表征模式下工作时，传输门和预充电电路被关断。 差分电压感测装置将表征信号应用于感测放大器，并通过试错过程获得存储器电路的参数。

公开(公告)号：US08723265B2

公开(公告)日：2014-05-13

申请号：US13158133

申请日：2011-06-10

申请人： Yen-Huei Chen ,  Wei Min Chan ,  Shao-Yu Chou ,  Hung-Jen Liao

发明人： Yen-Huei Chen ,  Wei Min Chan ,  Shao-Yu Chou ,  Hung-Jen Liao

IPC分类号： H01L21/70 ,  H01L27/32

CPC分类号： H01L27/0207 ,  H01L27/088 ,  H01L27/1104

摘要： A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions.

摘要翻译： 多指结构包括放置在一对虚拟POLY线之间的多个有源区域。 有源区域包括多个多指状NMOS晶体管，它们是SRAM存储器电路的读出放大器的一部分。 每个多指尖的NMOS晶体管的漏极和源极具有SiP / SiC外延生长区域。 有源区域与虚拟POLY线路延伸并重叠。 有源区域和虚拟POLY线之间的重叠有助于减少有源区域边缘处的边缘缺陷。

公开(公告)号：US08610236B2

公开(公告)日：2013-12-17

申请号：US12851702

申请日：2010-08-06

申请人： Yen-Huei Chen ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Hung-Jen Liao ,  Li-Chun Tien

发明人： Yen-Huei Chen ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Hung-Jen Liao ,  Li-Chun Tien

IPC分类号： H01L27/08

CPC分类号： H01L21/28008 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

摘要： A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.

摘要翻译： 字线驱动器包括具有沿半导体衬底的第一方向延伸的长度的有源区。 多个指状物形成在有源区域的上表面上。 多个指状物中的每一个具有在第二方向上延伸的长度，并且形成具有有效区域的一部分的MOS晶体管。 第一虚设结构设置在多个指状物的外部之一和半导体衬底的边缘之间。 第一虚拟结构包括至少部分地设置在有效区域的一部分上的部分。