SYSTEM AND METHOD TO GENERATE PRIME NUMBERS IN CRYPTOGRAPHIC APPLICATIONS

    公开(公告)号:US20220085998A1

    公开(公告)日:2022-03-17

    申请号:US17447122

    申请日:2021-09-08

    Abstract: Aspects of the present disclosure involve a method, a system and a computer readable memory to generate and use prime numbers in cryptographic operations by determining one or more polynomial functions that have no roots modulo each of a predefined set of prime numbers, selecting one or more input numbers, generating a candidate number by applying one or more instances of the one or more polynomial functions to the one or more input numbers, determining that the candidate number is a prime number, and using the determined prime number to decrypt an input into the cryptographic operation.

    GENERATING A KEY AT A DEVICE BASED ON A MEMORY OF THE DEVICE

    公开(公告)号:US20220006628A1

    公开(公告)日:2022-01-06

    申请号:US17305416

    申请日:2021-07-07

    Inventor: Helena Handschuh

    Abstract: An indication of a key generation function may be received from a server. A random value may be received based on a volatile memory of a device. A cryptographic key may be generated based on the key generation function from the server and the random value that is based on the volatile memory of the device. The cryptographic key may be stored at a non-volatile memory of the device.

    PROTECTING PARALLEL MULTIPLICATION OPERATIONS FROM EXTERNAL MONITORING ATTACKS

    公开(公告)号:US20210256165A1

    公开(公告)日:2021-08-19

    申请号:US17169074

    申请日:2021-02-05

    Abstract: Systems and methods for protecting from external monitoring attacks cryptographic data processing operations involving universal polynomial hash functions computation. An example method may comprise: receiving an input data block and an iteration result value; performing a first field multiplication operation to produce a new iteration result value, by iteratively processing, starting from a first bit position, bits of a combination of the input data block and the iteration result value, wherein the first bit position is represented by one of: a least-significant bit and a most-significant bit; performing a second field multiplication operation to produce a new mask correction value, by iteratively processing operand bits starting from a second bit position, wherein the second bit position is represented by one of: a least-significant bit and a most-significant bit, and wherein the second bit position is different from the first bit position; applying the new mask correction value to the new iteration result value; and producing, based on the new iteration result value, a value of a cryptographic hash function to be utilized by at least one of: an authenticated encryption operation or an authenticated decryption operation.

    MEMORY OPTIMIZATION FOR NESTED HASH OPERATIONS

    公开(公告)号:US20210226775A1

    公开(公告)日:2021-07-22

    申请号:US17248495

    申请日:2021-01-27

    Abstract: Disclosed is a method and a system to execute the method to perform a first hashing operation to compute a first hash value, store the first hash value in a plurality of output registers, store a second message in a plurality of input registers, perform a first iteration of a second hashing operation, with an input to the second hashing operation including the second message and the first hash value, determine that a first portion of the second message, stored in a first register of the plurality of input registers, has been processed in course of the second hashing operation, and move a first portion of the first hash value stored in a first register of the plurality of output registers to the first register of the plurality of input registers.

    Generating a key at a device based on a memory of the device

    公开(公告)号:US11063755B2

    公开(公告)日:2021-07-13

    申请号:US16405065

    申请日:2019-05-07

    Inventor: Helena Handschuh

    Abstract: An indication of a key generation function may be received from a server. A random value may be received based on a volatile memory of a device. A cryptographic key may be generated based on the key generation function from the server and the random value that is based on the volatile memory of the device. The cryptographic key may be stored at a non-volatile memory of the device.

    CRYPTOGRAPHIC MANAGEMENT OF LIFECYCLE STATES

    公开(公告)号:US20210160063A1

    公开(公告)日:2021-05-27

    申请号:US17119513

    申请日:2020-12-11

    Abstract: A secret key value that is inaccessible to software is scrambled according to registers consisting of one-time programmable (OTP) bits. A first OTP register is used to change the scrambling of the secret key value whenever a lifecycle event occurs. A second OTP register is used to undo the change in the scrambling of the secret key. A third OTP register is used to affect a permanent change to the scrambling of the secret key. The scrambled values of the secret key (whether changed or unchanged) are used as seeds to produce keys for cryptographic operations by a device.

    Self-test of an asynchronous circuit

    公开(公告)号:US10884058B2

    公开(公告)日:2021-01-05

    申请号:US15903980

    申请日:2018-02-23

    Abstract: An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal.

    Self-timed random number generator
    30.
    发明授权

    公开(公告)号:US10754620B2

    公开(公告)日:2020-08-25

    申请号:US16707349

    申请日:2019-12-09

    Inventor: Scott C. Best

    Abstract: The embodiments described herein describe technologies of self-timed pattern generators. The self-timed pattern generators can be used to form a random number generator to generate a random digital value. Asynchronous digital logic in a first generator asynchronously updates a next state based on a current state, a second state of a second generator that is before the first generator in the chain or ring topology, and a third state of a third generator that is after the first generator in the chain or ring topology. The self-timed pattern generators are to output a random digital value based at least in part on the current state output from the first generator.

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