Poly-chromatic light-emitting diode (LED) lighting system
    21.
    发明授权
    Poly-chromatic light-emitting diode (LED) lighting system 有权
    多色发光二极管(LED)照明系统

    公开(公告)号:US08188683B2

    公开(公告)日:2012-05-29

    申请号:US12805658

    申请日:2010-08-12

    CPC classification number: H05B33/086 H05B33/0866 H05B33/0872

    Abstract: The invention discloses a novel control system for a Poly-Chromatic light-emitting diode (LED) lighting system, and applies feed forward and feedback control techniques to regulate the color and luminous outputs. Also, the control system is proposed for achieving luminous and color consistency for Poly-Chromatic LED lighting.

    Abstract translation: 本发明公开了一种用于多色发光二极管(LED)照明系统的新型控制系统,并且使用前馈和反馈控制技术来调节颜色和发光输出。 此外,为了实现多色LED照明的发光和颜色一致性,提出了控制系统。

    Vibration control of an optical table by disturbance response decoupling
    22.
    发明申请
    Vibration control of an optical table by disturbance response decoupling 审中-公开
    通过扰动响应解耦对光学平台进行振动控制

    公开(公告)号:US20110133049A1

    公开(公告)日:2011-06-09

    申请号:US12801520

    申请日:2010-06-14

    CPC classification number: G05D19/02 F16F15/002

    Abstract: This invention discloses an optical table and the vibration control method thereof. Using disturbance response decomposing techniques, a double-layer structure is applied to independently control the ground and load disturbances. This invention can simplify the vibration control and improve system performance.

    Abstract translation: 本发明公开了一种光学台及其振动控制方法。 使用扰动响应分解技术,应用双层结构来独立控制地面和负载扰动。 本发明可以简化振动控制,提高系统性能。

    Fabrication of field-effect transistor for alleviating short-channel effects
    23.
    发明授权
    Fabrication of field-effect transistor for alleviating short-channel effects 有权
    用于减轻短沟道效应的场效晶体管的制造

    公开(公告)号:US06599804B2

    公开(公告)日:2003-07-29

    申请号:US09947012

    申请日:2001-09-04

    Abstract: Short-channel threshold voltage roll-off and punchthrough in an IGFET (40 or 42) having a channel zone (64 or 84) situated in body material (50) are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

    Abstract translation: 通过设置通道区域中的净掺杂剂浓度以纵向到达,减轻了具有位于主体材料(50)中的通道区(64或84)的IGFET(40或42)中的短通道阈值电压滚降和穿通 在IGFET源极/漏极区(60和62或80和82)之间的位置处的局部表面最小值,并且通过布置主体材料中的净掺杂剂浓度达到超过0.1μm深的主体材料的局部地下最大值 但不超过0.4 mum深入身材。

    Use of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors
    24.
    发明授权
    Use of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors 有权
    在制作不对称场效应晶体管时使用掩模阴影和角度注入

    公开(公告)号:US06566204B1

    公开(公告)日:2003-05-20

    申请号:US09540734

    申请日:2000-03-31

    Abstract: To furnish an IGFET (120 or 122) with an asymmetrically doped channel zone (144 or 164), a mask (212) is provided over a semiconductor body and an overlying electrically insulated gate electrode (148P or 168P). Ions of a semiconductor dopant species are directed toward an opening (213) in the mask from two different angular orientations along paths that originate laterally beyond opposite respective opening-defined sides of the mask. The location and shape of the opening are controlled so that largely only ions impinging from one of the angular orientations enter the intended location for the channel zone. Ions impinging from the other angular orientation are shadowed by the mask from entering the channel zone location. Although the ions impinging from this other angular orientation do not significantly dope the channel zone location, they normally enter the semiconductor body elsewhere, e.g., the intended location for the channel zone of another IGFET.

    Abstract translation: 为了提供具有不对称掺杂沟道区(144或164)的IGFET(120或122),掩模(212)设置在半导体主体和上覆电绝缘栅电极(148P或168P)上。 半导体掺杂剂物质的离子通过沿着路径的两个不同的角度取向指向掩模中的开口(213),该路径横向超过掩模的相对的开口限定侧。 控制开口的位置和形状,使得很大程度上只有从角度定向中的一个入射的离子进入通道区域的预期位置。 从另一个角度方向入射的离子被掩模遮蔽进入通道区位置。 尽管从该另一角度方向入射的离子不会显着地掺杂通道区位置,但是它们通常进入其它地方的半导体体,例如另一IGFET的沟道区的预期位置。

    Electrical control light valve apparatus having liquid metal
    26.
    发明申请
    Electrical control light valve apparatus having liquid metal 有权
    具有液态金属的电控光阀装置

    公开(公告)号:US20110194165A1

    公开(公告)日:2011-08-11

    申请号:US12805545

    申请日:2010-08-05

    CPC classification number: G02B26/004

    Abstract: The present invention discloses an electrical control light valve apparatus having liquid gallium. The invention comprises the transparent glass as a substrate, ITO transparent conductive film as the electrodes, the liquid gallium as the valve located on the ITO transparent conductive film, and the partial-transparent glass is located on the top of the electrical control light valve apparatus.

    Abstract translation: 本发明公开了一种具有液态镓的电控光阀装置。 本发明包括作为基板的透明玻璃,作为电极的ITO透明导电膜,作为阀的液态镓位于ITO透明导电膜上,部分透明玻璃位于电动控制光阀装置的顶部 。

    Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length
    27.
    发明授权
    Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length 有权
    具有减小的结电容和阈值电压的场效应晶体管的制造随着沟道长度的增加而减小

    公开(公告)号:US07879669B1

    公开(公告)日:2011-02-01

    申请号:US11527265

    申请日:2006-09-25

    Abstract: At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 μm greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 μm greater than LC.

    Abstract translation: 提供增强型绝缘栅场效应晶体管(120或122)的至少一个源极/漏极区(140,142,160或162)具有渐变结特征以减小结电容,从而提高开关速度。 每个分级接点源极/漏极区域包含主要部分(140M,142M,160M或162M)和在主要部分下面并垂直连续的较轻掺杂的下部分(140L,142L,160L或162L)。 在通道长度为LC时,在相同布局前制造工艺条件下制造的一组这样的晶体管的阈值电压的幅度达到最大绝对值VTAM至少为0.03 当沟道长度比LC大约0.3μm时,小于VTAM的伏特,并且当沟道长度大于LC时大约1.0μm时,随着沟道长度的增加而实质上减小。

    Signal Processing Apparatus for Multi-mode Satellite Positioning System and Method Thereof
    28.
    发明申请
    Signal Processing Apparatus for Multi-mode Satellite Positioning System and Method Thereof 有权
    多模卫星定位系统信号处理装置及方法

    公开(公告)号:US20100302100A1

    公开(公告)日:2010-12-02

    申请号:US12719294

    申请日:2010-03-08

    CPC classification number: G01S19/36 G01S19/33

    Abstract: A signal processing apparatus for a multi-mode satellite positioning system includes a band-pass filter, a local oscillator circuit, a first mixing circuit, a second mixing circuit, an analog-to-digital converter and a baseband circuit. By properly allocating a local frequency, radio frequency (RF) signals of a Global Positioning System (GPS), a Galileo positioning system and a Global Navigation System (GLONASS) are processed via a single signal path to save hardware cost.

    Abstract translation: 一种用于多模式卫星定位系统的信号处理装置,包括带通滤波器,本地振荡器电路,第一混频电路,第二混频电路,模数转换器和基带电路。 通过适当地分配本地频率,通过单个信号路径处理全球定位系统(GPS),伽利略定位系统和全球导航系统(GLONASS)的射频(RF)信号以节省硬件成本。

    Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics
    29.
    发明授权
    Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics 有权
    其中类似极性绝缘栅场效应晶体管具有多个垂直体掺杂浓度最大值和不同晕圈特征的半导体结构

    公开(公告)号:US07701005B1

    公开(公告)日:2010-04-20

    申请号:US11974751

    申请日:2007-10-15

    Abstract: Each of a pair of differently configured like-polarity insulated-gate field-effect transistors (40 or 42 and 240 or 242) in a semiconductor structure has a channel zone of semiconductor body material, a gate dielectric layer overlying the channel zone, and a gate electrode overlying the gate dielectric layer. For each transistor, the net dopant concentration of the body material reaches multiple local subsurface maxima below a channel surface depletion region and below largely all gate-electrode material overlying the channel zone. The transistors have source/drain zones (60 or 80) of opposite conductivity type to, and halo pocket portions of the same conductivity type as, the body material. One pocket portion (100/102 or 104) extends along both source/drain zones of one of the transistors. Another pocket portion (244 or 246) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.

    Abstract translation: 半导体结构中的一对不同构造的相同极性的绝缘栅场效应晶体管(40或42和240或242)中的每一个具有半导体主体材料的沟道区,覆盖沟道区的栅介质层和 覆盖栅介电层的栅电极。 对于每个晶体管,主体材料的净掺杂剂浓度在沟道表面耗尽区下方达到多个局部地下极大值,并且大部分覆盖在沟道区上方的所有栅电极材料。 晶体管具有与主体材料相同的导电类型的源极/漏极区域(60或80)以及与主体材料相同的导电类型的卤素口袋部分。 一个口袋部分(100/102或104)沿着一个晶体管的源极/漏极区域延伸。 另一个口袋部分(244或246)沿着另一个晶体管的源极/漏极区域中的一个较大地延伸,使得它是不对称的。

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