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    Configuration and fabrication of semiconductor structure using empty and filled wells
    1.
    发明授权
    Configuration and fabrication of semiconductor structure using empty and filled wells 有权
    使用空和填充井的半导体结构的配置和制造

    公开(公告)号：US08304835B2

    公开(公告)日：2012-11-06

    申请号：US12382973

    申请日：2009-03-27

    申请人： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

    发明人： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

    IPC分类号： H01L29/36

    CPC分类号： H01L27/088 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

    摘要翻译： 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管（IGFET）不同地使用的空阱区域和填充阱区域的组合，以实现期望的电子 特点 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET（100,102,112,114,124和126）利用空井（180,182,192,194,204和206）实现期望的晶体管特性。 其它IGFET（108,110,116,118,120和122）利用填充的孔（188,190,196,198,200和202）实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET，电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用，包括混合信号应用。

    Configuration and fabrication of semiconductor structure using empty and filled wells
    2.
    发明申请
    Configuration and fabrication of semiconductor structure using empty and filled wells 有权
    使用空和填充井的半导体结构的配置和制造

    公开(公告)号：US20100244128A1

    公开(公告)日：2010-09-30

    申请号：US12382973

    申请日：2009-03-27

    申请人： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

    发明人： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8238

    CPC分类号： H01L27/088 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

    摘要翻译： 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管（“IGFET”）不同地使用的空阱区域和填充阱区域的组合，以实现 所需的电子特性。 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET（100,102,112,114,124和126）利用空井（180,182,192,194,204和206）实现期望的晶体管特性。 其它IGFET（108,110,116,118,120和122）利用填充的孔（188,190,196,198,200和202）实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET，电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用，包括混合信号应用。

    Fabrication of field-effect transistor for alleviating short-channel effects
    3.
    发明授权
    Fabrication of field-effect transistor for alleviating short-channel effects 有权
    用于减轻短沟道效应的场效晶体管的制造

    公开(公告)号：US06599804B2

    公开(公告)日：2003-07-29

    申请号：US09947012

    申请日：2001-09-04

    申请人： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

    发明人： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

    IPC分类号： H01L21336

    CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/665

    摘要： Short-channel threshold voltage roll-off and punchthrough in an IGFET (40 or 42) having a channel zone (64 or 84) situated in body material (50) are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

    摘要翻译： 通过设置通道区域中的净掺杂剂浓度以纵向到达，减轻了具有位于主体材料（50）中的通道区（64或84）的IGFET（40或42）中的短通道阈值电压滚降和穿通 在IGFET源极/漏极区（60和62或80和82）之间的位置处的局部表面最小值，并且通过布置主体材料中的净掺杂剂浓度达到超过0.1μm深的主体材料的局部地下最大值 但不超过0.4 mum深入身材。

    Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length
    6.
    发明授权
    Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length 有权
    具有减小的结电容和阈值电压的场效应晶体管的制造随着沟道长度的增加而减小

    公开(公告)号：US07879669B1

    公开(公告)日：2011-02-01

    申请号：US11527265

    申请日：2006-09-25

    申请人： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

    发明人： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

    IPC分类号： H01L29/78

    CPC分类号： H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

    摘要： At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 μm greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 μm greater than LC.

    摘要翻译： 提供增强型绝缘栅场效应晶体管（120或122）的至少一个源极/漏极区（140,142,160或162）具有渐变结特征以减小结电容，从而提高开关速度。 每个分级接点源极/漏极区域包含主要部分（140M，142M，160M或162M）和在主要部分下面并垂直连续的较轻掺杂的下部分（140L，142L，160L或162L）。 在通道长度为LC时，在相同布局前制造工艺条件下制造的一组这样的晶体管的阈值电压的幅度达到最大绝对值VTAM至少为0.03 当沟道长度比LC大约0.3μm时，小于VTAM的伏特，并且当沟道长度大于LC时大约1.0μm时，随着沟道长度的增加而实质上减小。

    Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays
    7.
    发明授权
    Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays 有权
    监测过程失准的方法，以减少不对称器件的工作，并改善LDMOS晶体管阵列的电气和热载流子性能

    公开(公告)号：US07718448B1

    公开(公告)日：2010-05-18

    申请号：US11139819

    申请日：2005-05-27

    申请人： Douglas Brisbin ,  Prasad Chaparala

    发明人： Douglas Brisbin ,  Prasad Chaparala

    IPC分类号： G01R31/26 ,  G06F17/18 ,  G06F17/50

    CPC分类号： H01L22/34 ,  H01L29/7835

    摘要： A number of modified lateral DMOS (LDMOS) transistor arrays are formed and tested to determine if a measured value, such as a series on-resistance, substrate current, breakdown voltage, and reliability, satisfies process alignment requirements. The modified LDMOS transistor arrays are similar to standard LDMOS transistor arrays such that the results of the modified LDMOS transistor arrays can be used to predict the results of the standard LDMOS transistor arrays.

    摘要翻译： 形成并测试了许多改进的横向DMOS（LDMOS）晶体管阵列，以确定诸如串联导通电阻，衬底电流，击穿电压和可靠性的测量值是否满足工艺对准要求。 修改后的LDMOS晶体管阵列类似于标准LDMOS晶体管阵列，使得修改后的LDMOS晶体管阵列的结果可用于预测标准LDMOS晶体管阵列的结果。

    Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics
    8.
    发明授权
    Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics 有权
    其中类似极性绝缘栅场效应晶体管具有多个垂直体掺杂浓度最大值和不同晕圈特征的半导体结构

    公开(公告)号：US07701005B1

    公开(公告)日：2010-04-20

    申请号：US11974751

    申请日：2007-10-15

    申请人： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

    发明人： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

    IPC分类号： H01L29/80

    CPC分类号： H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

    摘要： Each of a pair of differently configured like-polarity insulated-gate field-effect transistors (40 or 42 and 240 or 242) in a semiconductor structure has a channel zone of semiconductor body material, a gate dielectric layer overlying the channel zone, and a gate electrode overlying the gate dielectric layer. For each transistor, the net dopant concentration of the body material reaches multiple local subsurface maxima below a channel surface depletion region and below largely all gate-electrode material overlying the channel zone. The transistors have source/drain zones (60 or 80) of opposite conductivity type to, and halo pocket portions of the same conductivity type as, the body material. One pocket portion (100/102 or 104) extends along both source/drain zones of one of the transistors. Another pocket portion (244 or 246) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.

    摘要翻译： 半导体结构中的一对不同构造的相同极性的绝缘栅场效应晶体管（40或42和240或242）中的每一个具有半导体主体材料的沟道区，覆盖沟道区的栅介质层和 覆盖栅介电层的栅电极。 对于每个晶体管，主体材料的净掺杂剂浓度在沟道表面耗尽区下方达到多个局部地下极大值，并且大部分覆盖在沟道区上方的所有栅电极材料。 晶体管具有与主体材料相同的导电类型的源极/漏极区域（60或80）以及与主体材料相同的导电类型的卤素口袋部分。 一个口袋部分（100/102或104）沿着一个晶体管的源极/漏极区域延伸。 另一个口袋部分（244或246）沿着另一个晶体管的源极/漏极区域中的一个较大地延伸，使得它是不对称的。

    Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction Capacitance
    9.
    发明申请
    Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction Capacitance 审中-公开
    用于缓解短沟道效应和/或降低结电容的场效晶体管的结构和制造

    公开(公告)号：US20120181614A1

    公开(公告)日：2012-07-19

    申请号：US13309473

    申请日：2011-12-01

    申请人： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

    发明人： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

    IPC分类号： H01L27/088

    CPC分类号： H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

    摘要： An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 μm deep into the body material but not more than 0.1 μm deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

    摘要翻译： IGFET（40或42）具有位于主体材料（50）中的通道区（64或84）。 通过设置通道区域中的净掺杂剂浓度以在IGFET的源极/漏极区域（60和62或80和82）之间的位置处纵向达到局部表面最小值来减轻短通道阈值电压滚降和穿透，以及 通过排列主体材料中的净掺杂剂浓度达到主体材料深度超过0.1μm的局部表面最大深度，但不超过体积材料的0.1μm深。 p沟道IGFET（120或122）的源极/漏极区（140和142或160和162）具有渐变结特征以减小结电容，从而提高开关速度。