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    Implementing Efuse sense amplifier testing without blowing the Efuse
    21.
    发明授权
    Implementing Efuse sense amplifier testing without blowing the Efuse 失效
    实现Efuse感应放大器测试，不会吹动Efuse

    公开(公告)号：US07689950B2

    公开(公告)日：2010-03-30

    申请号：US11872763

    申请日：2007-10-16

    申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

    发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

    IPC分类号： G06F17/50

    CPC分类号： G11C17/18 ,  G01R31/07 ,  G11C17/165 ,  G11C29/02 ,  G11C29/026 ,  G11C29/027

    摘要： A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

    摘要翻译： 一种用于eFuse的读出放大器的有效测试的方法和装置，而不必对eFuse进行编程或打击，并且提供了一个设在该电路中的设计结构。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。

    APPARATUS FOR IMPLEMENTING EFUSE SENSE AMPLIFIER TESTING WITHOUT BLOWING THE EFUSE
    23.
    发明申请
    APPARATUS FOR IMPLEMENTING EFUSE SENSE AMPLIFIER TESTING WITHOUT BLOWING THE EFUSE 失效
    用于实现EFUSE感应放大器测试的设备，而不会吹拂EFUSE

    公开(公告)号：US20090175106A1

    公开(公告)日：2009-07-09

    申请号：US12351908

    申请日：2009-01-12

    申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

    发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

    IPC分类号： G11C29/00 ,  G11C7/06 ,  G11C17/16

    CPC分类号： G11C29/12 ,  G11C17/165 ,  G11C17/18 ,  G11C29/026 ,  G11C29/027

    摘要： Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

    摘要翻译： 设备可实现对eFuse的读出放大器的有效测试，而无需对eFuse进行编程或打击。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。

    Redundancy circuit for memory array and method for disabling non-redundant wordlines and for enabling redundant wordlines
    24.
    发明授权
    Redundancy circuit for memory array and method for disabling non-redundant wordlines and for enabling redundant wordlines 失效
    用于存储器阵列的冗余电路和用于禁用非冗余字线和用于启用冗余字线的方法

    公开(公告)号：US06928009B2

    公开(公告)日：2005-08-09

    申请号：US10600064

    申请日：2003-06-20

    申请人： Chad Allen Adams ,  Gregory John Uhlmann

    发明人： Chad Allen Adams ,  Gregory John Uhlmann

    IPC分类号： G11C7/00 ,  G11C29/00

    CPC分类号： G11C29/70

    摘要： A redundancy circuit for a memory array and a method are provided for disabling non-redundant wordlines and for enabling redundant wordlines. A memory defect address is compared with a current address to be accessed. When there is a miscompare, the access to a non-redundant wordline is allowed to take place as normal. When the memory defect address matches the current address the entire wordline decoder is deactivated through a reset signal and the redundant wordline is activated.

    摘要翻译： 提供了用于存储器阵列的冗余电路和方法，用于禁用非冗余字线和用于启用冗余字线。 将存储器缺陷地址与要访问的当前地址进行比较。 当有错误的比较时，允许访问非冗余字线正常进行。 当存储器缺陷地址与当前地址匹配时，整个字线解码器通过复位信号被去激活，冗余字线被激活。

    Device and method for verifying independent reads and writes in a memory array
    25.
    发明授权
    Device and method for verifying independent reads and writes in a memory array 失效
    用于验证存储器阵列中的独立读和写的设备和方法

    公开(公告)号：US5973971A

    公开(公告)日：1999-10-26

    申请号：US2341

    申请日：1998-01-02

    申请人： Salvatore Nicholas Storino ,  Gregory John Uhlmann

    发明人： Salvatore Nicholas Storino ,  Gregory John Uhlmann

    IPC分类号： G01R31/28 ,  G11C29/34 ,  G11C29/36 ,  G11C29/00

    CPC分类号： G11C29/36

    摘要： A device and method for verifying independent reads and writes in a memory array includes bit inserters in the array to simultaneously insert a predetermined value into multiple portions of the array. Each row may have a corresponding row bit inserter. Alternatively, or in addition, each memory cell may have a storage element bit inserter. A row bit inserter places a predetermined value at the inputs of a row write port. The storage element bit inserters pre-set memory cells to a predetermined value. To test the read circuitry, storage element bit inserters are set to a predetermined value, and a read is performed. If the value read from a memory cell does not match the value to which it was set, it can be inferred that the read circuitry is not functioning properly. If the values match, it can be inferred that the read circuitry is functioning properly. To test the write circuitry, a row bit inserter may be set to a predetermined value. A write is performed, followed by a read. If the value read from a memory cell matches the value to which the row bit inserter was set, it can be inferred that the write circuitry is functioning properly. If the values do not match, and if it has already been determined that the read circuitry is functioning properly, it can be inferred that the write circuitry is not functioning properly.

    摘要翻译： 用于验证存储器阵列中的独立读和写的装置和方法包括阵列中的位插入器，以将预定值同时插入阵列的多个部分。 每行可以具有相应的行位插入器。 或者或另外，每个存储器单元可以具有存储元件位插入器。 行位插入器将预定值放置在行写入端口的输入端。 存储元件位插入器将存储器单元预先设定为预定值。 为了测试读取电路，将存储元件位插入器设置为预定值，并执行读取。 如果从存储单元读取的值与其设置的值不匹配，则可以推断读取电路不能正常工作。 如果值匹配，则可以推断读取电路正常工作。 为了测试写入电路，可以将行位插入器设置为预定值。 执行写操作，然后进行读取。 如果从存储单元读取的值与设置了行位插入器的值相匹配，则可以推断写入电路正常工作。 如果值不匹配，并且如果已经确定读取电路正常工作，则可以推断出写入电路不能正常工作。

    Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse
    27.
    发明授权
    Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse 失效
    用于实现eFuse读出放大器测试的设备，而不会吹动eFuse

    公开(公告)号：US07733722B2

    公开(公告)日：2010-06-08

    申请号：US12351908

    申请日：2009-01-12

    申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

    发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

    IPC分类号： G11C7/00

    CPC分类号： G11C29/12 ,  G11C17/165 ,  G11C17/18 ,  G11C29/026 ,  G11C29/027

    摘要： Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

    摘要翻译： 设备可实现对eFuse的读出放大器的有效测试，而无需对eFuse进行编程或打击。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。

    Method and Circuit for Implementing Enhanced Efuse Sense Circuit
    30.
    发明申请
    Method and Circuit for Implementing Enhanced Efuse Sense Circuit 失效
    实现增强型感应电路的方法和电路

    公开(公告)号：US20090201756A1

    公开(公告)日：2009-08-13

    申请号：US12029010

    申请日：2008-02-11

    申请人： Anthony Gus Aipperspach ,  Phil Christopher Paone ,  Brian Joy Reed ,  David Edward Schmitt ,  Gregory John Uhlmann

    发明人： Anthony Gus Aipperspach ,  Phil Christopher Paone ,  Brian Joy Reed ,  David Edward Schmitt ,  Gregory John Uhlmann

    IPC分类号： G11C7/00 ,  G11C17/18

    CPC分类号： G11C17/18 ,  G11C7/062 ,  G11C7/065 ,  G11C17/16 ,  G11C29/026

    摘要： A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.

    摘要翻译： 一种用于实现eFuse读出放大器的方法和电路，以及设置有被摄体电路的设计结构。 感测电路包括一对交叉耦合的反相器，每个由一对串联的P沟道场效应晶体管（PFET）和N沟道场效应晶体管（NFET）形成。 第一上拉电阻耦合在正电压供电轨和感测电路的第一感测节点之间。 第二上拉电阻耦合在感测电路的正电压供电轨道和第二感测节点之间。 第一位线耦合到感测电路的第一感测节点，耦合到感测电路的第二感测节点的第二位线。 相应的参考电阻器和相应的eFuse单元之一选择性地耦合到第一位线和第二位线。