公开(公告)号：US07528646B2

公开(公告)日：2009-05-05

申请号：US11550960

申请日：2006-10-19

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Phil Paone ,  David Edward Schmitt ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Phil Paone ,  David Edward Schmitt ,  Gregory John Uhlmann

IPC分类号： H01H37/76 ,  H01H85/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A electrically programmable fuse sense circuit having an electrically programmable fuse and a reference resistance. A first current source is coupled, through a first switch, to the electrically programmable fuse. A second current source is coupled, through a second switch, to the reference resistance. A precharge signal enables the first current source, the second current source and closes the first switch and the second switch, creating voltage drops across the electrically programmable fuse and the reference resistance. When the precharge signal goes inactive, the first current source and the second current source are shut off, and, at the same time the first switch and the second switch are opened. A latching circuit uses a difference in the voltage drops when the precharge signal goes inactive to store a state of the electrically programmable fuse, indicative of whether the electrically programmable fuse is blown or unblown.

摘要翻译： 一种具有电可编程熔丝和参考电阻的电可编程熔丝检测电路。 第一电流源通过第一开关耦合到电可编程保险丝。 第二电流源通过第二开关耦合到参考电阻。 预充电信号使得第一电流源，第二电流源能够闭合第一开关和第二开关，从而在电可编程保险丝和参考电阻之间产生电压降。 当预充电信号不起作用时，第一电流源和第二电流源被切断，同时第一开关和第二开关断开。 当预充电信号无效以存储电可编程熔丝的状态时，锁存电路使用电压降的差异，指示电可编程熔丝是否被吹制或未被吹出。

公开(公告)号：US07489572B2

公开(公告)日：2009-02-10

申请号：US11622519

申请日：2007-01-12

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

IPC分类号： G11C7/00

CPC分类号： G11C29/12 ,  G11C17/165 ,  G11C17/18 ,  G11C29/026 ,  G11C29/027

摘要： A method implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

摘要翻译： 一种方法实现对eFuse的读出放大器的有效测试，而不必对eFuse进行编程或打击。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。

公开(公告)号：US20080266735A1

公开(公告)日：2008-10-30

申请号：US11739723

申请日：2007-04-25

申请人： Phil C. Paone ,  David Paul Paulsen ,  John Edward Sheets ,  Gregory John Uhlmann

发明人： Phil C. Paone ,  David Paul Paulsen ,  John Edward Sheets ,  Gregory John Uhlmann

IPC分类号： H02H3/20

CPC分类号： G06F1/26

摘要： A method and apparatus implement adaptive power supply (APS) system voltage level activation eliminating the use of electronic Fuses (eFuses). A primary chip includes an adaptive power supply (APS). A secondary chip circuit includes at least one pair of hard-wired APS setting connections. Each hard-wired APS setting connection is defined by a selected one of a voltage supply connection and a ground potential connection. A respective inverter couples a control signal from each of the hard-wired APS setting connections to a power communication bus connected to the APS on the primary chip.

摘要翻译： 一种方法和装置实现自适应电源（APS）系统电压电平激活，消除使用电子保险丝（eFuses）。 主要芯片包括自适应电源（APS）。 二级芯片电路包括至少一对硬连接的APS设置连接。 每个硬接线APS设置连接由电压供应连接和地电位连接中选定的一个来定义。 相应的反相器将来自每个硬接线APS设置连接的控制信号耦合到连接到主芯片上的APS的电力通信总线。

公开(公告)号：US20080170449A1

公开(公告)日：2008-07-17

申请号：US11622519

申请日：2007-01-12

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

IPC分类号： G11C29/00

CPC分类号： G11C29/12 ,  G11C17/165 ,  G11C17/18 ,  G11C29/026 ,  G11C29/027

摘要： A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

摘要翻译： 一种用于eFuse的读出放大器的有效测试的方法和装置，而不必对eFuse进行编程或打击。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。

公开(公告)号：US07203518B2

公开(公告)日：2007-04-10

申请号：US09789283

申请日：2001-02-20

申请人： Salvatore Nicholas Storino ,  Gregory John Uhlmann

发明人： Salvatore Nicholas Storino ,  Gregory John Uhlmann

IPC分类号： H04Q7/20

CPC分类号： H04W28/14 ,  G06F2205/064

摘要： A wireless data retrieval device and method for implementing the same. In accordance with one embodiment of the invention, the wireless data retrieval device includes a first-in-first-out (FIFO) memory queue in the form of a linked list that stores standardized correspondence information. The wireless data retrieval device further includes an input/output device configured to transmit the standardized correspondence information to and receive said standardized correspondence information from a wireless channel.

摘要翻译： 一种无线数据检索装置及其实现方法。 根据本发明的一个实施例，无线数据检索装置包括存储标准对应信息的链表形式的先进先出（FIFO）存储器队列。 无线数据检索装置还包括被配置为将标准化对应信息发送到无线信道并从无线信道接收所述标准化对应信息的输入/输出装置。

公开(公告)号：US06629236B1

公开(公告)日：2003-09-30

申请号：US09439581

申请日：1999-11-12

申请人： Anthony Gus Aipperspach ,  Merwin Herscher Alferness ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  Merwin Herscher Alferness ,  Gregory John Uhlmann

IPC分类号： G06F938

CPC分类号： G06F9/30141 ,  G06F9/30116 ,  G06F9/3851

摘要： A master-slave latch circuit for a multithreaded processor stores information for multiple threads. The basic cell contains multiple master elements, each corresponding to a respective thread, selection logic coupled to the master elements for selecting a single one of the master outputs, and a single slave element coupled to the selector logic. Preferably, the circuit supports operation in a scan mode for testing purposes. In scan mode, one or more elements which normally function as master elements, function as slave elements. When operating in scan mode using this arrangement, the number of master elements in the pair of cells equals the number of slave elements, even though the number of master elements exceeds the number of slave elements during normal operation, permitting data to be successively scanned through all elements of the circuit. In an alternative embodiment, elements function as in scan mode during a HOLD mode of operation, and a feedback loop controlled by a HOLD signal is added to each pair of master/slave elements. The feedback loop drives the master element with the value of the slave.

摘要翻译： 用于多线程处理器的主从锁存电路存储多线程的信息。 基本单元包含多个主元件，每个主元件对应于相应的线程，耦合到主元件的选择逻辑用于选择主输出中的单个一个，以及耦合到选择器逻辑的单个从元件。 优选地，电路支持扫描模式下的操作用于测试目的。 在扫描模式中，通常用作主元件的一个或多个元件用作从元件。 当使用这种布置在扫描模式下操作时，即使在正常操作期间主元件的数量超过从元件的数量，一对单元中的主元件的数量等于从元件的数量，允许数据被连续地扫描通过 电路的所有元素。 在替代实施例中，元件在保持操作模式期间起到扫描模式的作用，并且将由HOLD信号控制的反馈回路添加到每对主/从元件。 反馈回路以从机的值驱动主元件。

公开(公告)号：US06498057B1

公开(公告)日：2002-12-24

申请号：US10092748

申请日：2002-03-07

申请人： Todd Alan Christensen ,  John Edward Sheets, II ,  Gregory John Uhlmann

发明人： Todd Alan Christensen ,  John Edward Sheets, II ,  Gregory John Uhlmann

IPC分类号： H01L2100

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84

摘要： Methods and silicon-on-Insulator (SOI) semiconductor structures are provided for implementing transistor source connections for SOI transistor devices using buried dual rall distribution. A SOI semiconductor structure Includes a SOI transistor having a silicide layer covering a SOI transistor source, a predefined burled conduction layer to be connected to a SOI transistor source, and an Intermediate conduction layer between the SOI transistor and the predefined buried conduction layer, A first hole for a transistor source connection to a local interconnect is anisotropically etched in the SOI semiconductor structure to the silcide layer covering the SOI transistor source. A second hole aligned with the local interconnect hole is anisotropically etched through the SOI semiconductor structure to the predefined buried conduction layer. An Insulator is disposed between the second hole and the intermediate conduction layer. A conductor Is deposited in the first and second holes to create a transistor source connection to the predefined burled conduction layer In the SOI semiconductor structure.

摘要翻译： 提供了方法和绝缘体上硅（SOI）半导体结构，用于实现使用掩埋双球面分布的SOI晶体管器件的晶体管源极连接。 SOI半导体结构包括具有覆盖SOI晶体管源的硅化物层的SOI晶体管，要连接到SOI晶体管源的预定义的烧制导电层，以及SOI晶体管和预定义的掩埋导电层之间的中间导电层，A第一 用于与局部互连的晶体管源极连接的孔在SOI半导体结构中被各向异性地蚀刻到覆盖SOI晶体管源的硅化物层。 与局部互连孔对准的第二孔通过SOI半导体结构被各向异性蚀刻到预定义的掩埋导电层。 绝缘体设置在第二孔和中间导电层之间。 在SOI半导体结构中，导体沉积在第一和第二孔中以产生到预定义的透明导电层的晶体管源极连接。

公开(公告)号：US06211713B1

公开(公告)日：2001-04-03

申请号：US09305774

申请日：1999-04-27

申请人： Gregory John Uhlmann

发明人： Gregory John Uhlmann

IPC分类号： H03K3356

CPC分类号： H03K3/012 ,  H03K3/037

摘要： An improved latch circuit having a dynamically adjustable internal feedback level. The improved latch circuit includes a latch inverter and a feedback inverter cross-coupled with the latch inverter. A controllable supplemental feedback inverter is connected in parallel with the feedback inverter to provide a controllable level of feedback to the latch inverter. An independently selectable control signal enables or disables the controllable feedback inverter in conformity with a need for more or less feedback, such that the internal feedback level may provide optimal functionality and performance of the latch circuit.

摘要翻译： 一种具有动态可调内部反馈电平的改进的锁存电路。 改进的锁存电路包括锁存逆变器和与锁存逆变器交叉耦合的反馈反相器。 可控补充反馈逆变器与反馈逆变器并联连接，为锁存逆变器提供可控的反馈水平。 可独立选择的控制信号根据对或多或少反馈的需要启用或禁用可控反馈逆变器，使得内部反馈电平可以提供锁存电路的最佳功能和性能。

公开(公告)号：US6163173A

公开(公告)日：2000-12-19

申请号：US305704

申请日：1999-05-05

申请人： Salvatore N. Storino ,  Gregory John Uhlmann ,  Robert Russell Williams

发明人： Salvatore N. Storino ,  Gregory John Uhlmann ,  Robert Russell Williams

IPC分类号： H03K19/00 ,  H03K19/096 ,  H03K19/96

CPC分类号： H03K19/0963 ,  H03K19/0027

摘要： Methods and apparatus are provided for implementing adjustable logic threshold in dynamic circuits. The dynamic circuit includes an intermediate precharge node. An output logic stage is connected to the intermediate precharge node. A threshold adjustment circuit is connected to the output logic stage. The threshold adjustment circuit receives a selection input to adjust a threshold of the output logic stage. The threshold adjustment circuit is formed of a first transistor and a second transistor coupled in parallel with a pair of series connected transistors included in the output logic stage. One or both of the first transistor and second transistor are selectively activated to adjust the threshold of the output logic stage.

摘要翻译： 提供了用于在动态电路中实现可调逻辑阈值的方法和装置。 动态电路包括中间预充电节点。 输出逻辑级连接到中间预充电节点。 阈值调整电路连接到输出逻辑级。 阈值调整电路接收选择输入以调整输出逻辑级的阈值。 阈值调节电路由与输出逻辑级中包括的一对串联连接的晶体管并联耦合的第一晶体管和第二晶体管构成。 选择性地激活第一晶体管和第二晶体管中的一个或两个以调整输出逻辑级的阈值。

公开(公告)号：US07224633B1

公开(公告)日：2007-05-29

申请号：US11297311

申请日：2005-12-08

申请人： William Paul Hovis ,  Alan James Leslie ,  Phil Paone ,  David W. Siljenberg ,  Salvatore Nicholas Storino ,  Gregory John Uhlmann

发明人： William Paul Hovis ,  Alan James Leslie ,  Phil Paone ,  David W. Siljenberg ,  Salvatore Nicholas Storino ,  Gregory John Uhlmann

IPC分类号： G11C17/18

CPC分类号： G11C17/18

摘要： An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.

摘要翻译： 芯片上的eFuse参考单元提供的参考电压大于由芯片上具有未引脚eFuse的eFuse单元产生的最小电压，但小于由芯片上具有熔丝eFuse的eFuse单元产生的最小电压。 参考电流流过eFuse参考电池中的电阻和非吹出eFuse，产生参考电压。 参考电压用于在eFuse单元中创建参考电流的镜像副本。 参考电流的镜像副本通过eFuse单元中的eFuse流动。 比较器接收参考电压和eFuse单元产生的电压。 比较器产生一个响应于eFuse电池与参考电压相比产生的电压的输出逻辑电平。