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公开(公告)号：US20240298473A1
公开(公告)日：2024-09-05
申请号：US18025538
申请日：2022-05-30
Inventor： Wenbin Jia
IPC: H10K59/122 , H10K59/12 , H10K59/35 , H10K71/13
CPC classification number: H10K59/122 , H10K59/1201 , H10K59/353 , H10K71/135
Abstract: A display panel and a method for manufacturing the same, and a displaying device, which relates to the technical field of displaying. The display panel includes a substrate base plate, and a pixel definition layer. The pixel definition layer is configured for defining a plurality of sub-pixel openings, and includes: primary pixel blocking walls and a plurality of sub-pixel blocking walls that intersect. The plurality of sub-pixel blocking walls include first sub-pixel blocking walls and second sub-pixel blocking walls, both of heights of the first sub-pixel blocking walls and heights of the second sub-pixel blocking walls are less than heights of the primary pixel blocking walls, and the first sub-pixel blocking walls and the second sub-pixel blocking walls have different heights and/or different materials.
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公开(公告)号：US20240292663A1
公开(公告)日：2024-08-29
申请号：US18022998
申请日：2022-04-25
Inventor： Huifeng WANG
IPC: H10K59/122 , H10K59/121 , H10K59/80 , H10K102/00
CPC classification number: H10K59/122 , H10K59/1213 , H10K59/80515 , H10K59/874 , H10K2102/351
Abstract: A display substrate and a display apparatus. The display substrate includes: a base and a pixel definition layer arranged on a side of the base, the pixel definition layer includes: a first definition layer and a second definition layer located on a side of the first definition layer away from the base, the first definition layer includes: a plurality of first definition structures arranged in an array, the second definition layer includes: a plurality of second definition structures arranged at intervals in a first direction, wherein a plurality of first definition structures located between two adjacent second definition structures are arranged at intervals in a second direction, and an orthographic projection of a first definition structure on the base is separated from an orthographic projection of a second definition structure on the base, the second direction intersects the first direction.
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公开(公告)号：US12062318B2
公开(公告)日：2024-08-13
申请号：US17766696
申请日：2021-06-29
IPC: G09G3/20 , G09G3/3233
CPC classification number: G09G3/2096 , G09G3/2074 , G09G3/3233 , G09G2300/0842 , G09G2320/0233 , G09G2360/16
Abstract: A method for driving a display panel is provided. The method includes receiving image data of a frame of image, the image data including a plurality of initial grayscale values respectively for a plurality of subpixels in the display panel; and converting the image data into a converted image data including a plurality of converted grayscale values respectively for the plurality of subpixels. Converting the image data includes compensating a respective initial grayscale value for a respective subpixel by at least a respective delay-compensating factor to obtain a respective converted grayscale value. With respect to a p-th subpixel and a q-th subpixel respectively connected to a respective data line and having a same initial grayscale values, a p-th delay-compensating factor for the p-th subpixel is greater than a q-th delay-compensating factor for the q-th subpixel.
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公开(公告)号：US20240233650A1
公开(公告)日：2024-07-11
申请号：US17921677
申请日：2021-11-08
Inventor： Zhidong YUAN , Yongqian LI , Pan XU , Can YUAN
IPC: G09G3/3266 , G09G3/20 , G09G3/3233 , G11C19/28
CPC classification number: G09G3/3266 , G09G3/2096 , G09G3/3233 , G11C19/28 , G09G2300/0819 , G09G2300/0842 , G09G2310/0286 , G09G2310/08 , G09G2340/00
Abstract: A light-emitting control shift register includes an input circuit, a pulse width adjustment circuit, a pull-up circuit, a pull-down control circuit and a pull-down circuit. The input circuit is configured to output a signal of a first signal input terminal. The pulse width adjustment circuit is configured to transmit the signal output from the input circuit to a pull-up node, and is further configured to output a signal of a second clock signal terminal to the pull-up node. The pull-up circuit is configured to output a voltage of a first voltage terminal to a signal output terminal. The pull-down control circuit is configured to output the voltage of the first voltage terminal, and is further configured to output a voltage of a second voltage terminal. The pull-down circuit is configured to pull down a voltage of the signal output terminal to the voltage of the second voltage terminal.
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公开(公告)号：US20240203357A1
公开(公告)日：2024-06-20
申请号：US17802580
申请日：2021-04-01
Inventor： Xuehuan FENG , Yongqian LI , Pan XU
IPC: G09G3/3266 , G11C19/28
CPC classification number: G09G3/3266 , G11C19/28 , G09G2300/0426 , G09G2300/0842 , G09G2310/0286 , G09G2310/08
Abstract: A display panel has a display area and a fan-out region. The display panel includes: a substrate; a scan driving circuit including shift registers and clock signal lines, sub-pixels and signal transmission lines that are located in the display area; and a power supply voltage bus and connection lines that are located in the fan-out region. The sub-pixels are arranged in rows and columns, sub-pixels in a column are arranged along a second direction. A signal transmission line is electrically connected to column(s) of sub-pixels. The connection lines include first connection sub-lines, second connection sub-lines and third connection sub-lines that extend along the second direction and are located away from the sub-pixels. A first connection sub-line, a second connection sub-line and a third connection sub-line are electrically connected to the signal transmission line, the power supply voltage bus, and a clock signal line, respectively.
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Patent Agency Ranking
公开(公告)号：US11985864B2
公开(公告)日：2024-05-14
申请号：US17506532
申请日：2021-10-20
Inventor： Xinxin Wang , Minghung Hsu
IPC: H01L27/32 , H01L51/56 , H10K50/824 , H10K59/122 , H10K71/00 , H10K59/12
CPC classification number: H10K59/122 , H10K50/824 , H10K71/00 , H10K59/1201
Abstract: Provided is a display panel, including: a backplane; a first electrode and an auxiliary layer, disposed on a same side of the backplane, wherein a distance between a surface of the first electrode distal from the backplane and the backplane is shorter than or equal to a distance between a surface of the auxiliary layer distal from the backplane and the backplane; a pixel defining layer, at least partially disposed on a side of the auxiliary layer distal from the backplane; a second electrode, disposed on a side of the pixel defining layer distal from the backplane; and an auxiliary electrode, disposed on a side of the second electrode distal from the backplane, wherein an orthographic projection of the auxiliary electrode onto the backplane is located within an orthographic projection of the pixel defining layer onto the backplane.
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公开(公告)号：US11955089B2
公开(公告)日：2024-04-09
申请号：US17680956
申请日：2022-02-25
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan , Pan Xu
IPC: G09G3/3275 , H10K59/131
CPC classification number: G09G3/3275 , H10K59/131 , G09G2310/061
Abstract: Provided is a display substrate. The display substrate includes two pixels arranged along a first direction and adjacent to each other on a base substrate, and a pixel circuit in each of the two pixels includes a drive transistor, a first reset transistor, and a second reset transistor. A display device is also provided.
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公开(公告)号：US20240090270A1
公开(公告)日：2024-03-14
申请号：US18272014
申请日：2021-11-26
Inventor： Huifeng WANG
IPC: H10K59/122 , H10K59/12 , H10K59/80
CPC classification number: H10K59/122 , H10K59/1201 , H10K59/80522
Abstract: An embodiment of the present disclosure relates to a display panel including a pixel definition layer which includes a plurality of first pixel definition strips extending in a first direction and arranged at intervals in a second direction perpendicular to the first direction; a plurality of second pixel definition strips extending in the second direction and arranged at intervals in the first direction, wherein at least one of the plurality of second pixel definition strips has at least one widened part which has a width greater than a width of the remaining part of the second pixel definition strip, wherein the width of the widened part is a maximum width of a cross-section of the widened part; and an auxiliary electrode hole disposed in the at least one widened parts. Embodiments of the present disclosure further relate to a display device and a method for preparing a display panel.
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公开(公告)号：US20240087516A1
公开(公告)日：2024-03-14
申请号：US17767757
申请日：2021-05-13
Inventor： Can YUAN , Yongqian LI , Zhidong YUAN
IPC: G09G3/3233 , G09G3/3266 , H10K59/131
CPC classification number: G09G3/3233 , G09G3/3266 , H10K59/131 , G09G2310/061 , G09G2320/0204
Abstract: Provided is a display substrate, including: a base substrate; a plurality of sub-pixels arranged in an array on the base substrate, each of the sub-pixels including a light-emitting drive circuit, a reset circuit, a compensation circuit and a light-emitting element; wherein the light-emitting drive circuit and the reset circuit are connected to the light-emitting element, the light-emitting drive circuit is configured to provide a drive signal to the light-emitting element, and the reset circuit is configured to provide a reset signal to the light-emitting element; the compensation circuit is connected to the light-emitting drive circuit, and the compensation circuit is configured to provide a compensation signal to the light-emitting drive circuit; wherein at least two of the sub-pixels share a same target circuit, and the target circuit includes at least one of the reset circuit and the compensation circuit.
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公开(公告)号：US11929022B2
公开(公告)日：2024-03-12
申请号：US17641991
申请日：2021-05-18
Inventor： Zhidong Yuan , Yongqian Li , Can Yuan
IPC: G09G3/3225
CPC classification number: G09G3/3225 , G09G2310/0297 , G09G2310/08
Abstract: The present disclosure provides a multiplexing circuitry, a multiplexing method, a multiplexing module, and a display device. The multiplexing circuitry includes N multiplexing unit circuitries, N energy storage unit circuitries and N control unit circuitries. An nth multiplexing unit circuitry is configured to enable an nth output data line to be electrically coupled to or electrically decoupled from an input data line under the control of a potential at an nth control end; an nth energy storage unit circuitry is configured to control a potential at the nth control end in accordance with an nth clock signal; and an nth control unit circuitry is configured to enable the nth control end to be electrically coupled to or electrically decoupled from an nth switch control line in accordance with a control voltage signal and an nth switch control signal.
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