公开(公告)号：US20060242501A1

公开(公告)日：2006-10-26

申请号：US11343210

申请日：2006-01-31

Applicant: Paul Kimelman ,  Edmond Ashfield ,  Thomas Houlihane ,  Ian Field

Inventor： Paul Kimelman ,  Edmond Ashfield ,  Thomas Houlihane ,  Ian Field

IPC: G01R31/28

CPC classification number: G06F13/4282 ,  G01R31/31713 ,  G01R31/318572

Abstract: An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals.

Abstract translation: 集成电路设置有诸如串行扫描链或调试总线访问电路的诊断电路，通过使用与到外部诊断装置的双向串行链路耦合的接口电路来建立通信。 双向串行链路携带数据和控制信号。

公开(公告)号：US07080178B2

公开(公告)日：2006-07-18

申请号：US10773452

申请日：2004-02-09

Applicant: Paul Kimelman ,  Ian Field

Inventor： Paul Kimelman ,  Ian Field

IPC: G06F13/24 ,  G06F13/26

CPC classification number: G06F13/26

Abstract: A data processing system nested interrupt controller 24 responsive to priority level values 28, 30 associated with respective interrupt handling programs to control the execution of those interrupt handling programs. The priority level values have a first portion 28 which controls whether or not a pending interrupt handling program will pre-empt an already active interrupt handling program and a second portion 30 which controls which of a plurality of pending interrupt handling programs will be executed next when they share the same value for the first portion of their priority level value.

Abstract translation: 数据处理系统嵌套中断控制器24响应于与各个中断处理程序相关联的优先级值28,30，以控制这些中断处理程序的执行。 优先级值具有第一部分28，该第一部分28控制待决中断处理程序是否将预先占用已经活动的中断处理程序，而第二部分30控制下一个将执行多个待处理的中断处理程序中的哪一个， 它们对于其优先级值的第一部分共享相同的值。

公开(公告)号：US20050177691A1

公开(公告)日：2005-08-11

申请号：US10773453

申请日：2004-02-09

Applicant: Paul Kimelman ,  Ian Field

Inventor： Paul Kimelman ,  Ian Field

IPC: G06F9/34 ,  G06F12/02 ,  G06F12/04 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/04

Abstract: A data processing system 2 has a base data address region 24 and a bit-band data address region 28. Memory accesses to the bit-band data address region 28 are converted into memory accesses to the base data address region 24. In the process of this conversion specific bits within the base data address region 24 are picked out for access whether that be via a read-modify-write operation or a masked read operation as appropriate. In this way, bit access is provided to data values within the base data address region 24 by addressing specific address locations within the bit-band data address region 28.

Abstract translation: 数据处理系统2具有基本数据地址区域24和位带数据地址区域28。 对位带数据地址区域28的存储器访问被转换为对基本数据地址区域24的存储器访问。 在该转换过程中，基本数据地址区域24中的特定位被拾取用于存取，无论是通过读取 - 修改 - 写入操作还是适当的掩蔽读取操作。 以这种方式，通过寻址位数据地址区域28内的特定地址位置，向基数据地址区域24内的数据值提供位访问。