公开(公告)号：US08112560B2

公开(公告)日：2012-02-07

申请号：US12805913

申请日：2010-08-24

Applicant: Paul Kimelman ,  Edmond John Simon Ashfield ,  Steven Richard Mellor ,  Ian Field

Inventor： Paul Kimelman ,  Edmond John Simon Ashfield ,  Steven Richard Mellor ,  Ian Field

IPC: G06F13/28 ,  G06F13/36

CPC classification number: G06F13/28

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract translation: 公开了一种用于控制多个数据源与多个数据目的地之间的数据传输的直接存储器存取控制器。 多个数据源和数据目的地经由多个通道与直接存储器访问控制器通信，直接存储器访问控制器还与存储器和处理器进行通信。 存储器存储用于多个通道中的每个通道和处理器的两组控制数据。 直接存储器存取控制器响应于从所述多个通道中的一个或从所述处理器接收的数据传输请求，以访问存储在所述存储器中的一组所述对应控制数据，所述直接存储器访问执行所述数据的至少一部分 根据所访问的控制数据请求传送。

公开(公告)号：US07243206B2

公开(公告)日：2007-07-10

申请号：US10412693

申请日：2003-04-14

Applicant: Paul Kimelman ,  Ian Field

Inventor： Paul Kimelman ,  Ian Field

IPC: G06F12/12

CPC classification number: G06F9/342 ,  G06F9/30181 ,  G06F12/0638 ,  G06F2212/2022

Abstract: A method and data processing apparatus for remapping selected data access requests issued by a processor for accessing data items stored on a ROM. The method comprises the following steps: storing at least one replacement data item corresponding to at least one data item and different to said at least one data item in a portion of a RAM memory block, said RAM memory block being accessible by said processor, and said portion having been defined for storage of said at least one replacement data item; intercepting a data access request from said processor to said ROM; comparing at least a portion of an address of said intercepted data access request with a stored at least one identifier, said stored at least one identifier identifying an address of at least one data item stored on said ROM, and depending on said comparison either: remapping said data access request to said RAM memory block, such that a replacement data item stored on said memory block is accessed if said comparison indicates said at least a portion of an address to correspond to an address identified by said at least one identifier; or if said comparison indicates said at least a portion of an address not to be an address identified by said at least one stored identifier accessing a data item located at a position corresponding to said address on said ROM.

Abstract translation: 一种用于重新映射由处理器发出的用于访问存储在ROM上的数据项的所选择的数据访问请求的方法和数据处理装置。 该方法包括以下步骤：在RAM存储器块的一部分中存储至少一个对应于至少一个数据项并且与所述至少一个数据项不同的替换数据项，所述RAM存储块可由所述处理器访问，以及 所述部分已经被定义用于存储所述至少一个替换数据项; 截取从所述处理器到所述ROM的数据访问请求; 将所述截取的数据访问请求的地址的至少一部分与存储的至少一个标识符进行比较，所述存储的至少一个标识符识别存储在所述RO​​M上的至少一个数据项的地址，并且根据所述比较：重新映射 所述数据访问请求到所述RAM存储器块，使得如果所述比较指示地址的所述至少一部分对应于由所述至少一个标识符标识的地址，则访问存储在所述存储器块上的替换数据项; 或者如果所述比较指示所述地址的至少一部分不是由所述至少一个存储的标识符识别的地址，其访问位于与所述ROM上的所述地址相对应的位置的数据项。

公开(公告)号：US20050034017A1

公开(公告)日：2005-02-10

申请号：US10633363

申请日：2003-08-04

Applicant: Cedric Airaud ,  Nicholas Smith ,  Paul Kimelman ,  Ian Field ,  Man Yiu ,  David McHale ,  Andrew Swaine

Inventor： Cedric Airaud ,  Nicholas Smith ,  Paul Kimelman ,  Ian Field ,  Man Yiu ,  David McHale ,  Andrew Swaine

IPC: G06F11/28 ,  G06F9/48 ,  G06F11/07 ,  G06F11/27 ,  G06F11/30 ,  H05K10/00

CPC classification number: G06F11/366 ,  G06F11/2242 ,  G06F11/3632 ,  G06F11/3636

Abstract: A data processing apparatus controls cross-triggering of diagnostic processes on a plurality of processing devices. The data processing apparatus comprises a routing module having a plurality of broadcast channels, one or more of the broadcast channels being operable to indicate the occurrence of a diagnostic event on one or more of the plurality of processing devices. The data processing apparatus also comprises an mapping module associated with a corresponding processing device. The interface module programmably asserts diagnostic event signals from the associated processing device to one or more of the plurality of broadcast channels and programmably retrieves diagnostic events signals from processing devices other than the associated processing device from one or more of the plurality of broadcast channels. The retrieved diagnostic event data is used to facilitate triggering of a diagnostic process on the associated processing device in dependence upon said retrieved diagnostic event data.

Abstract translation: 数据处理装置控制多个处理装置上的诊断处理的交叉触发。 数据处理装置包括具有多个广播信道的路由模块，一个或多个广播信道可操作以指示在多个处理设备中的一个或多个上发生诊断事件。 数据处理装置还包括与对应的处理装置相关联的映射模块。 接口模块可编程地将来自相关联的处理设备的诊断事件信号断言成多个广播信道中的一个或多个，并且可编程地从多个广播信道中的一个或多个处理装置处理除相关联的处理设备之外的处理设备的诊断事件信号。 所检索的诊断事件数据用于根据所检索的诊断事件数据来便利触发关联处理设备上的诊断过程。

公开(公告)号：US07805557B2

公开(公告)日：2010-09-28

申请号：US11178586

申请日：2005-07-12

Applicant: Paul Kimelman ,  Gary Campbell ,  Simon Axford ,  Ian Field

Inventor： Paul Kimelman ,  Gary Campbell ,  Simon Axford ,  Ian Field

IPC: G06F13/26

CPC classification number: G06F13/26

Abstract: An interrupt controller and method are provided for handling interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises pend logic for receiving interrupt requests generated by the plurality of interrupt sources, and for each interrupt request, determining whether to accept that interrupt request for handling by the interrupt controller. Interrupt handling logic then selects an interrupt request from amongst those interrupt requests accepted by the pend logic, and generates an indication of the interrupt routine to be executed by a processor to process that interrupt request. The pend logic is arranged, for each of the interrupt sources, to detect a transition of the associated interrupt request from an unset state to a set state, and to accept the interrupt request upon such detection. The pend logic also receives an exit signal indicating completion of the interrupt routine by the processor, and if the associated interrupt request is in the set state on receipt of the exit signal, re-accepts that interrupt request. By such an approach, the interrupt controller can automatically support both level interrupt requests and pulsed interrupt requests without the need for software configuration.

Abstract translation: 提供了一种用于处理由多个中断源产生的中断请求的中断控制器和方法。 中断控制器包括用于接收由多个中断源产生的中断请求的后置逻辑，并且对于每个中断请求，确定是否接受该中断请求以由中断控制器处理。 然后中断处理逻辑从由挂起逻辑接受的那些中断请求中选择一个中断请求，并产生处理该中断请求的由处理器执行的中断程序的指示。 对于每个中断源，配置逻辑以检测相关联的中断请求从未设置状态到设置状态的转换，并且在这种检测时接受中断请求。 挂机逻辑还接收指示处理器完成中断程序的退出信号，如果相关联的中断请求在接收到退出信号时处于置位状态，则重新接受该中断请求。 通过这种方法，中断控制器可以自动支持电平中断请求和脉冲中断请求，而无需软件配置。

公开(公告)号：US07444546B2

公开(公告)日：2008-10-28

申请号：US10417335

申请日：2003-04-17

Applicant: Paul Kimelman ,  Ian Field

Inventor： Paul Kimelman ,  Ian Field

IPC: G60F11/00

CPC classification number: G06F11/267 ,  G06F11/2733

Abstract: An integrated circuit having a plurality of functional circuits interconnected via a functional bus is provided with a diagnostic bus-master circuit which uses bus transactions on the functional bus to perform diagnostic operations. These diagnostic operations can be performed in real time during normal speed operation of the integrated circuit to produce more accurate diagnostic results. The diagnostic bus-master circuit is particularly useful for reading data values from memory or writing data values to memory as part of diagnostic operations.

Abstract translation: 具有通过功能总线互连的多个功能电路的集成电路设置有使用功能总线上的总线事务执行诊断操作的诊断总线主控电路。 这些诊断操作可以在集成电路的正常速度运行期间实时执行，以产生更准确的诊断结果。 诊断总线 - 主电路对于从存储器读取数据值或将数据值写入存储器作为诊断操作的一部分特别有用。

公开(公告)号：US07278073B2

公开(公告)日：2007-10-02

申请号：US10417329

申请日：2003-04-17

Applicant: Paul Kimelman ,  Ian Field

Inventor： Paul Kimelman ,  Ian Field

IPC: G01R31/28

CPC classification number: G01R31/31705

Abstract: An integrated circuit is provided with a diagnostic data capture and output system in the form of a diagnostic data capture circuit which captures a data word and a context word from a bus. The bus may be the functional bus connecting functional circuits within the integrated circuit or a dedicated bus linking one or more functional circuits directly to the diagnostic data capture circuit. The diagnostic data captured is buffered within a first-in-first-out buffer and then serialised for output. The diagnostic data fields also include a time value indicative of the time at which the diagnostic data field concerned was captured and whether any diagnostic data fields have failed to be captured.

Abstract translation: 集成电路具有以诊断数据捕获电路形式的诊断数据捕获和输出系统，其从总线捕获数据字和上下文字。 总线可以是连接集成电路内的功能电路的功能总线或将一个或多个功能电路直接连接到诊断数据捕获电路的专用总线。 捕获的诊断数据在先进先出缓冲区中缓冲，然后序列化以进行输出。 诊断数据字段还包括指示捕获诊断数据字段的时间的时间值以及是否有任何诊断数据字段被捕获。

公开(公告)号：US07206884B2

公开(公告)日：2007-04-17

申请号：US10775334

申请日：2004-02-11

Applicant: Paul Kimelman ,  Ian Field ,  Richard Roy Grisenthwaite

Inventor： Paul Kimelman ,  Ian Field ,  Richard Roy Grisenthwaite

IPC: G06F13/26

CPC classification number: G06F9/4818

Abstract: A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.

Abstract translation: 具有嵌套中断控制器24的数据处理系统2支持嵌套的活动中断。 与系统正在运行时，与不同中断关联的优先级别是可改变的（可能是可编程的）。 为了防止在嵌套中断中与优先级颠倒相关的问题，嵌套中断控制器在考虑暂挂中断是否应该预先占用现有的活动中断时，将待处理中断的优先级与任何当前活动中断的最高优先级进行比较， 嵌套在一起

公开(公告)号：US20070016710A1

公开(公告)日：2007-01-18

申请号：US11178586

申请日：2005-07-12

Applicant: Paul Kimelman ,  Gary Campbell ,  Simon Axford ,  Ian Field

Inventor： Paul Kimelman ,  Gary Campbell ,  Simon Axford ,  Ian Field

IPC: G06F13/26

CPC classification number: G06F13/26

Abstract: An interrupt controller and method are provided for handling interrupt requests generated by a plurality of interrupt sources. Th interrupt controller comprises pend logic for receiving interrupt requests generated by the plurality of interrupt sources, and for each interrupt request determining whether to accept that interrupt request for handling by the interrupt controller. Interrupt handling logic then selects an interrupt request from amongst those interrupt requests accepted by the pend logic, and generates an indication of the interrupt routine to be executed by a processor to process that interrupt request. The pend logic is arranged, for each of the interrupt sources, to detect a transition of the associated interrupt request from an unset state to a set state, and to accept the interrupt request upon such detection. The pend logic is also operable to receive an exit signal indicating completion of the interrupt routine by the processor, and if the associated interrupt request is in the set state on receipt of the exit signal, re-accepts that interrupt request. By such an approach, the interrupt controller can automatically support both level interrupt requests and pulsed interrupt requests without the need for software configuration.

Abstract translation: 提供了一种用于处理由多个中断源产生的中断请求的中断控制器和方法。 中断控制器包括用于接收由多个中断源产生的中断请求的挂起逻辑，并且针对每个中断请求确定是否接受该中断请求以由中断控制器处理。 然后中断处理逻辑从由挂起逻辑接受的那些中断请求中选择一个中断请求，并产生处理该中断请求的由处理器执行的中断程序的指示。 对于每个中断源，配置逻辑以检测相关联的中断请求从未设置状态到设置状态的转换，并且在这种检测时接受中断请求。 后端逻辑还可操作以接收指示处理器完成中断程序的退出信号，并且如果相关联的中断请求在接收到退出信号时处于置位状态，则重新接受该中断请求。 通过这种方法，中断控制器可以自动支持电平中断请求和脉冲中断请求，而无需软件配置。

公开(公告)号：US20050177668A1

公开(公告)日：2005-08-11

申请号：US10773452

申请日：2004-02-09

Applicant: Paul Kimelman ,  Ian Field

Inventor： Paul Kimelman ,  Ian Field

IPC: G06F13/26

CPC classification number: G06F13/26

Abstract: A data processing system nested interrupt controller 24 responsive to priority level values 28, 30 associated with respective interrupt handling programs to control the execution of those interrupt handling programs. The priority level values have a first portion 28 which controls whether or not a pending interrupt handling program will pre-empt an already active interrupt handling program and a second portion 30 which controls which of a plurality of pending interrupt handling programs will be executed next when they share the same value for the first portion of their priority level value.

Abstract translation: 数据处理系统嵌套中断控制器24响应于与各个中断处理程序相关联的优先级值28,30，以控制这些中断处理程序的执行。 优先级值具有第一部分28，该第一部分28控制待决中断处理程序是否将预先占用已经活动的中断处理程序，而第二部分30控制下一个将执行多个待处理的中断处理程序中的哪一个， 它们对于其优先级值的第一部分共享相同的值。

公开(公告)号：US20050177666A1

公开(公告)日：2005-08-11

申请号：US10775335

申请日：2004-02-11

Applicant: Paul Kimelman ,  Ian Field

Inventor： Paul Kimelman ,  Ian Field

IPC: G06F9/48 ,  G06F9/46 ,  G06F12/00

CPC classification number: G06F9/4818

Abstract: A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24. The interrupt controller is responsive to save state data when interrupt processing is commenced by pre-emption of existing processing, whether that be background processing or another interrupt. If a further interrupt is required to be executed immediately after the interrupt which triggered the pre-emption, then the speed with which interrupt processing can be started is advantageously increased if that subsequent interrupt processing is performed without restoring and then resaving the original state data. The interrupts in this arrangement can be considered to be chained together without intervening save and restore operations.

Abstract translation: 支持中断处理的数据处理系统2具有中断控制器24.中断控制器响应于通过抢占现有处理开始中断处理时的保存状态数据，无论是后台处理还是另一个中断。 如果在触发优先级的中断之后立即执行进一步的中断，则如果在不恢复并且然后重新保存原始状态数据的情况下执行后续中断处理，则有利地增加可以开始中断处理的速度。 这种安排的中断可以被认为是链接在一起的，而不需要进行保存和恢复操作。