公开(公告)号：US20070184336A1

公开(公告)日：2007-08-09

申请号：US11444320

申请日：2006-06-01

申请人： Ji-rae Kim ,  Seung-jae Lee ,  Jun-young Park ,  Hae-kwon Yoon ,  Joon-hyung Lee

发明人： Ji-rae Kim ,  Seung-jae Lee ,  Jun-young Park ,  Hae-kwon Yoon ,  Joon-hyung Lee

IPC分类号： H01M4/94 ,  H01M4/88

CPC分类号： H01M4/8896 ,  H01M4/8605 ,  H01M4/861 ,  H01M4/8807 ,  H01M4/881 ,  H01M4/8814 ,  H01M4/8817 ,  H01M8/04197 ,  H01M8/04291 ,  H01M8/1009 ,  H01M8/1011 ,  Y02E60/523 ,  Y02P70/56

摘要： A membrane electrode assembly for a fuel cell, a method of preparing the same, and a fuel cell using the membrane electrode assembly for a fuel cell. The membrane electrode assembly includes an anode comprising an anode substrate, an anode diffusion layer, and an anode catalyst layer having pores; a cathode comprising a cathode substrate, a cathode diffusion layer, and a cathode catalyst layer having pores; and an electrolyte membrane interposed between the cathode and the anode, wherein the anode diffusion layer is hydrophilic and the cathode diffusion layer is hydrophobic, and the average diameter of the pores of the anode catalyst layer is smaller than the average diameter of the pores of the cathode catalyst layer. In the membrane electrode assembly, air can be easily supplied to the cathode and water can easily flow out of the cathode, thereby obtaining high performance of the membrane electrode assembly, and the anode catalyst layer has relatively small pores, thereby improving durability of the anode and reducing the diffusion speed of methanol in the anode catalyst layer to maintain the initial performance of a battery for a long time.

摘要翻译： 用于燃料电池的膜电极组件，其制备方法和使用燃料电池用膜电极组件的燃料电池。 膜电极组件包括阳极，阳极包括阳极基底，阳极扩散层和具有孔的阳极催化剂层; 包括阴极衬底，阴极扩散层和具有孔的阴极催化剂层的阴极; 以及插入在所述阴极和所述阳极之间的电解质膜，其中所述阳极扩散层是亲水性的，并且所述阴极扩散层是疏水性的，并且所述阳极催化剂层的孔的平均直径小于所述阳极催化剂层的孔的平均直径 阴极催化剂层。 在膜电极组件中，可以容易地向阴极供给空气，水容易从阴极流出，从而获得膜电极组件的高性能，并且阳极催化剂层具有相对较小的孔，从而提高阳极的耐久性 并降低甲醇在阳极催化剂层中的扩散速度，以保持电池的初始性能很长时间。

公开(公告)号：US20060255369A1

公开(公告)日：2006-11-16

申请号：US11430580

申请日：2006-05-09

申请人： Yong-Chan Kim ,  Yong-Don Kim ,  Joon-Hyung Lee

发明人： Yong-Chan Kim ,  Yong-Don Kim ,  Joon-Hyung Lee

IPC分类号： H01L29/768

CPC分类号： H01L27/0922 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/66606 ,  H01L29/7836

摘要： A high-voltage semiconductor device and a method of manufacturing the high-voltage semiconductor device are provided. For example, with the above device and method drift regions having first depths are formed in a semiconductor substrate by doping first impurities. The drift regions are spaced apart from each other to define a channel region between the drift regions. Source/drain regions having second depths are formed at first portions of the drift regions by doping second impurities. Impurity accumulation regions having third depths are formed at second portions of the drift region adjacent to the source/drain regions by doping third impurities. A gate insulation layer pattern is formed on the semiconductor substrate to partially expose the source/drain regions. A gate conductive layer pattern is formed on a portion of the gate insulation layer pattern where the channel region is positioned. A buffer layer capable of preventing a rapid increase of a current is formed on the gate structure and the gate insulation layer pattern.

摘要翻译： 提供一种高压半导体器件和制造该高压半导体器件的方法。 例如，通过掺杂第一杂质，在半导体衬底中形成具有第一深度的上述器件和方法漂移区。 漂移区域彼此间隔开以限定漂移区域之间的沟道区域。 通过掺杂第二杂质在漂移区的第一部分处形成具有第二深度的源/漏区。 通过掺杂第三杂质，在与源极/漏极区相邻的漂移区的第二部分处形成具有第三深度的杂质聚集区。 在半导体衬底上形成栅极绝缘层图案以部分地暴露源极/漏极区域。 栅极导电层图案形成在栅极绝缘层图案的其中定位沟道区域的部分上。 在栅极结构和栅极绝缘层图案上形成能够防止电流快速增加的缓冲层。

公开(公告)号：US06885609B2

公开(公告)日：2005-04-26

申请号：US10724687

申请日：2003-12-02

申请人： Tae-jung Lee ,  Byung-sun Kim ,  Joon-hyung Lee

发明人： Tae-jung Lee ,  Byung-sun Kim ,  Joon-hyung Lee

IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C8/00 ,  G11C11/00

CPC分类号： G11C8/16

摘要： A layout of a memory cell of a dual-port semiconductor memory device provides for one memory cell that includes a total of eight transistors, including two NMOS scan transistors. Among the transistors, two PMOS transistors and six NMOS transistors are disposed in one N-well area and one contiguous P-well area of a semiconductor substrate, respectively. The N-well area is disposed at a corner of the memory cell for improving efficiency of the layout. Since one N-well area and one P-well area are formed in the semiconductor substrate, the size of an isolated area between the N-well area and the P-well area can be reduced, thus also reducing the size of a memory cell.

摘要翻译： 双端口半导体存储器件的存储单元的布局提供了一个存储单元，其包括总共八个晶体管，包括两个NMOS扫描晶体管。 在晶体管中，两个PMOS晶体管和六个NMOS晶体管分别设置在半导体衬底的一个N阱区域和一个邻接的P阱区域中。 N阱区域设置在存储单元的拐角处，以提高布局的效率。 由于在半导体衬底中形成一个N阱区和一个P阱区，所以可以减小N阱区和P阱区之间的隔离区的大小，从而也减小了存储单元的尺寸 。