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    Cell structure of EPROM device and method for fabricating the same
    3.
    发明授权
    Cell structure of EPROM device and method for fabricating the same 有权
    EPROM器件的单元结构及其制造方法

    公开(公告)号：US07348241B2

    公开(公告)日：2008-03-25

    申请号：US11384727

    申请日：2006-03-20

    申请人： Joon-hyung Lee ,  Byung-sun Kim ,  Tae-jung Lee

    发明人： Joon-hyung Lee ,  Byung-sun Kim ,  Tae-jung Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7881

    摘要： Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack. Thus, ultraviolet rays can penetrate through the window and easily erase charges of the programmed cell.

    摘要翻译： 提供EPROM器件的单元结构及其制造方法。 电池结构包括栅极堆叠，其包括第一浮置栅极，包括氮化物层的绝缘图案和顺序地堆叠在半导体衬底上的控制栅极，并且包括用于暴露所述顶部表面或两个侧壁的窗口 第一个浮动栅极位于控制栅极的两侧，使得第一个浮动栅极的电荷可以被紫外线消除。 电池结构还包括浮栅晶体管，其包括形成在半导体衬底上的栅极绝缘层，形成在栅极绝缘层上并连接到栅堆叠中的第一浮栅的第二浮栅，以及源极 /漏极，其形成在半导体衬底中以便与第二浮栅对准。 在电池结构中，窗口形成在栅堆叠的第一浮栅的顶表面或两个侧壁上。 因此，紫外线可以穿过窗口并容易地擦除编程单元的电荷。

    Cell structure of non-volatile memory device and method for fabricating the same
    4.
    发明授权
    Cell structure of non-volatile memory device and method for fabricating the same 失效

    公开(公告)号：US06995421B2

    公开(公告)日：2006-02-07

    申请号：US10621571

    申请日：2003-07-18

    申请人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    发明人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

    摘要： A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

    One-time programmable (OTP) memory cell and OTP memory device for multi-bit program
    5.
    发明授权
    One-time programmable (OTP) memory cell and OTP memory device for multi-bit program 有权
    一次性可编程（OTP）存储单元和用于多位程序的OTP存储器件

    公开(公告)号：US09524795B2

    公开(公告)日：2016-12-20

    申请号：US14847160

    申请日：2015-09-08

    申请人： Joon-Hyung Lee ,  Oh-Kyum Kwon

    发明人： Joon-Hyung Lee ,  Oh-Kyum Kwon

    IPC分类号： G11C17/16 ,  G11C17/18

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： A one-time programmable (OTP) memory device includes a memory cell array including a plurality of OTP memory cells, the plurality of OTP memory cells being connected to a plurality of bitlines, a plurality of voltage wordlines and a plurality of read wordlines, respectively; and a switching circuit configured to, in a program mode, detect program states of the plurality of OTP memory cells to block currents from flowing through the plurality of OTP memory cells from the voltage wordlines to the bitlines based on the detected program states.

    摘要翻译： 一次性可编程（OTP）存储器件包括包括多个OTP存储器单元的存储单元阵列，多个OTP存储器单元分别连接到多个位线，多个电压字线和多个读字线 ; 以及开关电路，被配置为在程序模式下，基于检测到的程序状态，检测多个OTP存储器单元的程序状态以阻止电流从电压字线流过多个OTP存储单元到位线。

    ONE-TIME PROGRAMMABLE (OTP) MEMORY CELL AND OTP MEMORY DEVICE FOR MULTI-BIT PROGRAM
    6.
    发明申请
    ONE-TIME PROGRAMMABLE (OTP) MEMORY CELL AND OTP MEMORY DEVICE FOR MULTI-BIT PROGRAM 有权
    用于多位程序的一次性可编程（OTP）存储器单元和OTP存储器件

    公开(公告)号：US20160148705A1

    公开(公告)日：2016-05-26

    申请号：US14847160

    申请日：2015-09-08

    申请人： Joon-Hyung LEE ,  Oh-Kyum KWON

    发明人： Joon-Hyung LEE ,  Oh-Kyum KWON

    IPC分类号： G11C17/18 ,  G11C17/16

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： A one-time programmable (OTP) memory device includes a memory cell array including a plurality of OTP memory cells, the plurality of OTP memory cells being connected to a plurality of bitlines, a plurality of voltage wordlines and a plurality of read wordlines, respectively; and a switching circuit configured to, in a program mode, detect program states of the plurality of OTP memory cells to block currents from flowing through the plurality of OTP memory cells from the voltage wordlines to the bitlines based on the detected program states.

    摘要翻译： 一次性可编程（OTP）存储器件包括包括多个OTP存储器单元的存储单元阵列，多个OTP存储器单元分别连接到多个位线，多个电压字线和多个读字线 ; 以及开关电路，被配置为在程序模式下，基于检测到的程序状态，检测多个OTP存储器单元的程序状态以阻止电流从电压字线流过多个OTP存储单元到位线。

    Dual port semiconductor memory device
    7.
    发明授权
    Dual port semiconductor memory device 有权
    双端口半导体存储器件

    公开(公告)号：US07120080B2

    公开(公告)日：2006-10-10

    申请号：US10751178

    申请日：2004-01-02

    申请人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    发明人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    IPC分类号： G11C8/00 ,  G11C5/06 ,  G11C11/00 ,  G06F12/00 ,  G06F13/28

    CPC分类号： H01L27/1104 ,  G09G3/3611 ,  G11C7/02 ,  G11C8/16 ,  G11C11/4125 ,  H01L27/11

    摘要： A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.

    摘要翻译： 提供了包括PMOS扫描晶体管的双端口半导体存储器件。 双端口半导体存储器件包括两个PMOS晶体管，两个NMOS下拉晶体管，两个NMOS传输晶体管和PMOS扫描晶体管。 作为PMOS的扫描晶体管，可以提高噪声容限。 此外，这七个晶体管排列在两个n阱和2个p阱中，而n阱和p阱以串联和交替的方式排列。 因此，沿着存储单元的短轴的存储单元的长度相对较短。 该存储单元布局通过将一对位线与阱边界并排布置，即在存储单元的短轴方向上有助于缩短位线的长度，并且可以防止位线与位线之间的串扰 通过在位线和互补位线之间布置导线来补充位线。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PERFORMING BURN-IN TEST ON THE SAME
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PERFORMING BURN-IN TEST ON THE SAME 有权
    半导体存储器件及其相同的测试方法

    公开(公告)号：US20130148405A1

    公开(公告)日：2013-06-13

    申请号：US13653782

    申请日：2012-10-17

    申请人： Sang-beom KANG ,  Joon-hyung LEE

    发明人： Sang-beom KANG ,  Joon-hyung LEE

    IPC分类号： G11C29/12 ,  G11C11/02 ,  G11C11/21

    CPC分类号： G11C29/08 ,  G11C5/06 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1697 ,  G11C13/00 ,  G11C16/10 ,  G11C29/12005 ,  G11C29/18 ,  G11C29/34 ,  G11C2029/1802

    摘要： A semiconductor memory device includes a cell array having a plurality of memory cells, each memory cell including a resistive element and a cell transistor between a bit line and a source line, and a source line voltage supply unit configured to supply, in a normal mode, a reference source line voltage to the source line, and in a test mode, a first source line voltage to the source line when data in a first state is recorded and a second source line voltage to the source line when data in a second state is recorded, the first source line voltage being lower than the reference source line voltage, and the second source line voltage being higher than the reference source line voltage.

    摘要翻译： 半导体存储器件包括具有多个存储单元的单元阵列，每个存储单元包括位线和源极线之间的电阻元件和单元晶体管，以及源极线电压供给单元，被配置为以正常模式 ，到源极线的参考源极线电压，并且在测试模式中，当记录处于第一状态的数据时，到源极线的第一源极线电压，以及当处于第二状态的数据时到源极线的第二源极线电压 ，第一源极线电压低于基准源极线电压，第二源极线电压高于基准源极线电压。