公开(公告)号：US5317197A

公开(公告)日：1994-05-31

申请号：US54901

申请日：1993-04-29

申请人： Martin C. Roberts

发明人： Martin C. Roberts

IPC分类号： H01L21/74 ,  H01L21/768 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L21/768 ,  H01L21/743 ,  H01L21/76895 ,  Y10S257/90 ,  Y10S257/904

摘要： A method of providing electrical contact between a gate of a transistor device and an active area remote of the transistor device includes: a) providing a first layer of a conductivity capable material over a gate insulative layer; b) etching the first layer and gate layer to expose a contact area; c) providing a second layer of a second material over the contact area and first layer; d) etching the second layer selectively relative to the first material and the substrate to provide a pair of buried contact spacers over respective opposing edges of the first layer in the contact area, and to reexpose a portion of the contact area and the first layer; e) providing a third layer of a conductivity capable material over the first layer, the buried contact spacers and the exposed portion of the contact area; f) etching the first and third layers to define a transistor gate of one device and a transistor gate of another device, and to interconnect the transistor gate of the another device to the portion of the contact area with the third layer material, and to define an exposed region adjacent both the one gate and one of the buried contact spacers; h) providing insulative spacers about edges of the transistor gates; i) providing a conductivity enhancing impurity implant into the substrate through the exposed region; j) rendering the portion of the contact area within the substrate electrically conductive; and k) rendering substrate beneath the one buried contact spacer electrically conductive to electrically interconnect the portion of the contact area within the substrate to the conductivity enhancing impurity implanted region of the substrate.

摘要翻译： 在晶体管器件的栅极和远离晶体管器件的有源区域之间提供电接触的方法包括：a）在栅极绝缘层上提供具有导电性的材料的第一层; b）蚀刻第一层和栅极层以暴露接触区域; c）在接触区域和第一层上提供第二材料的第二层; d）相对于所述第一材料和所述衬底选择性地蚀刻所述第二层，以在所述接触区域中的所述第一层的相应相对边缘上提供一对掩埋接触间隔物，并且重新接触所述接触区域和所述第一层的一部分; e）在所述第一层，所述埋入接触间隔物和所述接触区域的暴露部分上提供第三层导电性材料; f）蚀刻第一和第三层以限定一个器件的晶体管栅极和另​​一器件的晶体管栅极，并且将另一器件的晶体管栅极互连到与第三层材料的接触区域的部分，并且定义 与所述一个栅极和一个所述埋入式接触间隔物相邻的暴露区域; h）提供围绕晶体管栅极的边缘的绝缘间隔物; i）通过暴露区域向衬底提供增强电导率的杂质; j）使基板内的接触区域的部分导电; 并且k）在一个埋入式接触间隔物的下方呈现导电的衬底，以将衬底内的接触区域的部分电气互连到衬底的导电性增强杂质注入区域。

公开(公告)号：US5232863A

公开(公告)日：1993-08-03

申请号：US963836

申请日：1992-10-20

申请人： Martin C. Roberts

发明人： Martin C. Roberts

IPC分类号： H01L21/74 ,  H01L21/768

CPC分类号： H01L21/768 ,  H01L21/743 ,  H01L21/76895 ,  Y10S257/90 ,  Y10S257/904

摘要： A method of providing electrical contact between a gate of a transistor device and an active area remote of the transistor device includes: a) providing a first layer of a conductivity capable material over a gate insulative layer; b) etching the first and gate layers to expose a contact area; c) providing a second layer of a second material over the contact area and first layer; d) etching the second layer selectively relative to the first material and the substrate to provide a pair of buried contact spacers over respective opposing edges of the first layer in the contact area, and to reexpose a portion of the contact area and the first layer; e) providing a third layer of a conductivity capable material over the first layer, the buried contact spacers and the exposed portion of the contact area; f) etching the first and third layers to define a transistor gate of one device and a transistor gate of another device, and to interconnect the transistor gate of the another device to the portion of the contact area with the third layer material, and to define an exposed region adjacent both the one gate and one of the buried contact spacers; h) providing insulative spacers about edges of the transistor gates; i) providing a conductivity enhancing impurity implant into the substrate through the exposed region; j) rendering the portion of the contact area within the substrate electrically conductive; and k) rendering substrate beneath the one buried contact spacer electrically conductive to electrically interconnect the portion of the contact area within the substrate to the conductivity enhancing impurity implanted region of the substrate.

摘要翻译： 在晶体管器件的栅极和远离晶体管器件的有源区域之间提供电接触的方法包括：a）在栅极绝缘层上提供具有导电性的材料的第一层; b）蚀刻第一和栅极层以暴露接触区域; c）在接触区域和第一层上提供第二材料的第二层; d）相对于所述第一材料和所述衬底选择性地蚀刻所述第二层，以在所述接触区域中的所述第一层的相应相对边缘上提供一对掩埋接触间隔物，并且重新接触所述接触区域和所述第一层的一部分; e）在所述第一层，所述埋入接触间隔物和所述接触区域的暴露部分上提供第三层导电性材料; f）蚀刻第一和第三层以限定一个器件的晶体管栅极和另​​一器件的晶体管栅极，并且将另一器件的晶体管栅极互连到与第三层材料的接触区域的部分，并且定义 与所述一个栅极和一个所述埋入式接触间隔物相邻的暴露区域; h）提供围绕晶体管栅极的边缘的绝缘间隔物; i）通过暴露区域向衬底提供增强电导率的杂质; j）使基板内的接触区域的部分导电; 并且k）在一个埋入式接触间隔物的下方呈现导电的衬底，以将衬底内的接触区域的部分电气互连到衬底的导电性增强杂质注入区域。

公开(公告)号：US5118641A

公开(公告)日：1992-06-02

申请号：US581669

申请日：1990-09-13

申请人： Martin C. Roberts

发明人： Martin C. Roberts

IPC分类号： H01L21/32 ,  H01L21/762

CPC分类号： H01L21/76221 ,  H01L21/32

摘要： Methods for reducing encroachment of the field oxide into the active area on a silicon integrated circuit are disclosed. The present invention modifies the conventional LOCOS technique for forming active areas and field oxide areas on a silicon substrate. Rather than fully forming the field oxide regions immediately after the silicon nitride layer is patterned and etched on the substrate, a thin field oxide is grown. This oxide is partially wet etched to leave a ribbon of bare silicon around and extending under the edges of the silicon nitride mask. An additional nitride layer is deposited over the entire wafer and anisotropically etched to form a nitride spacer between the original nitride mask and the partially grown field oxide. The nitride spacer seals the edge of the active area by inhibiting the diffusion of oxygen under the nitride mask. During subsequent field oxidation, the nitride spacer greatly reduces the encroachment of the field oxide into the active area.

摘要翻译： 公开了减少场氧化物侵入硅集成电路中有源区的方法。 本发明修改了在硅衬底上形成有源区和场氧化物区的常规LOCOS技术。 在氮化硅层被图案化和蚀刻在衬底上之后，立即完全形成场氧化物区域，而是生长薄的场氧化物。 这种氧化物被部分湿蚀刻以在氮化硅掩模的边缘周围留下裸硅带并在其边缘延伸。 在整个晶片上沉积另外的氮化物层，并进行各向异性蚀刻，以在原始氮化物掩模和部分生长的场氧化物之间形成氮化物间隔物。 氮化物间隔物通过抑制氧化物掩模下的氧的扩散来密封有源区的边缘。 在随后的场氧化期间，氮化物间隔物大大减少了场氧化物侵入活性区域。