公开(公告)号：US09984934B2

公开(公告)日：2018-05-29

申请号：US15473699

申请日：2017-03-30

Applicant: Renesas Electronics Corporation

Inventor： Koji Maekawa ,  Tatsuyoshi Mihara

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/266 ,  H01L29/06 ,  H01L29/36

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/0615 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66553 ,  Y10S257/90 ,  Y10S438/90

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

公开(公告)号：US09780184B2

公开(公告)日：2017-10-03

申请号：US15165951

申请日：2016-05-26

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Kunal R. Parekh

IPC: H01L29/76 ,  H01L29/49 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8238

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S257/90

Abstract: The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.

公开(公告)号：US20170207128A1

公开(公告)日：2017-07-20

申请号：US15473699

申请日：2017-03-30

Applicant: Renesas Electronics Corporation

Inventor： Koji MAEKAWA ,  Tatsuyoshi MIHARA

IPC: H01L21/8234 ,  H01L29/36 ,  H01L21/266 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/0615 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66553 ,  Y10S257/90 ,  Y10S438/90

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

公开(公告)号：US20170117412A1

公开(公告)日：2017-04-27

申请号：US15377540

申请日：2016-12-13

Applicant: SOCIONEXT INC.

Inventor： Yosuke Shimamune ,  Akira Katakami ,  Akiyoshi Hatada ,  Masashi Shima ,  Naoyoshi Tamura

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/45 ,  H01L21/285 ,  H01L29/06 ,  H01L29/04 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28518 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  Y10S257/90

Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.

公开(公告)号：US09577098B2

公开(公告)日：2017-02-21

申请号：US15189581

申请日：2016-06-22

Applicant: SOCIONEXT INC.

Inventor： Yosuke Shimamune ,  Akira Katakami ,  Akiyoshi Hatada ,  Masashi Shima ,  Naoyoshi Tamura

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28518 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  Y10S257/90

Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.

Abstract translation: 一种半导体器件包括：栅极电极，形成在硅衬底上，栅极绝缘膜对应于沟道区，形成在硅衬底中的p型扩散区的源极和漏极区域的侧壁绝缘膜的相应外侧 栅电极和在硅衬底中在与硅衬底呈外延角的侧壁绝缘膜的各外侧形成的一对SiGe混合晶体区域，SiGe混晶区域由彼此相对的侧壁表面限定，其中 在每个SiGe混合晶体区域中，侧壁表面由相对于硅衬底的主表面形成相应不同角度的多个面限定。

公开(公告)号：US09368598B2

公开(公告)日：2016-06-14

申请号：US14560437

申请日：2014-12-04

Applicant: Renesas Electronics Corporation

Inventor： Koji Maekawa ,  Tatsuyoshi Mihara

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/0615 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66553 ,  Y10S257/90 ,  Y10S438/90

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

Abstract translation: 为了覆盖第一，第二和第三栅电极，在半导体衬底上形成绝缘膜和另一绝缘膜。 另一绝缘膜被回蚀刻以在绝缘膜的侧表面上形成侧壁间隔物。 然后，去除与第一和第二栅电极的侧壁相对应的绝缘膜的侧表面上的侧壁间隔物，以使侧壁间隔物超过对应于第三栅电极的侧壁的绝缘膜的侧表面。 然后，侧壁间隔物和绝缘膜被回蚀刻，使得侧壁间隔物由绝缘膜形成在第一，第二和第三栅电极的侧壁上。

公开(公告)号：US20150014789A1

公开(公告)日：2015-01-15

申请号：US14499834

申请日：2014-09-29

Applicant: Texas Instruments Incorporated

Inventor： Weize W. Xiong ,  Cloves R. Cleavelin ,  Angelo Pinto ,  Rick L. Wise

IPC: H01L27/088 ,  H01L27/11 ,  G11C11/412 ,  H01L29/04

CPC classification number: H01L27/0886 ,  G11C11/412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/045 ,  Y10S257/90 ,  Y10S438/973 ,  Y10S438/982

Abstract: An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orienations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.

Abstract translation: 公开了一种包括多个多栅极FinFET（MuGFET）的集成电路器件。 通过在直接硅键合（DSB）混合取向技术（HOT）衬底上的非晶化和晶体再生长形成用于PMOS和NMOS MuGFET的不同晶体取向的晶片。 PMOS MuGFET翅片由具有（110）晶体取向的翅片侧壁表面限定的通道形成。 NMOS MuGFET翅片由曼哈顿布局具有（100）晶体衍射的翅片侧壁表面限定的通道形成，其中不同PMOS和NMOS MuGFET的侧壁通道以0°或90°旋转对准。

公开(公告)号：US20140035057A1

公开(公告)日：2014-02-06

申请号：US13855520

申请日：2013-04-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Weize W. Xiong ,  Cloves R. Cleavelin ,  Angelo Pinto ,  Rick L. Wise

IPC: H01L27/11 ,  H01L27/092

CPC classification number: H01L27/0886 ,  G11C11/412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/045 ,  Y10S257/90 ,  Y10S438/973 ,  Y10S438/982

Abstract: An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.

Abstract translation: 公开了一种包括多个多栅极FinFET（MuGFET）的集成电路器件。 通过在直接硅键合（DSB）混合取向技术（HOT）衬底上的非晶化和晶体再生长形成用于PMOS和NMOS MuGFET的不同晶体取向的晶片。 PMOS MuGFET翅片由具有（110）晶体取向的翅片侧壁表面限定的通道形成。 NMOS MuGFET翅片由曼哈顿布局具有（100）晶体取向的翅片侧壁表面限定的通道形成，其中不同PMOS和NMOS MuGFET的侧壁通道以0°或90°旋转对准。

公开(公告)号：US08466450B2

公开(公告)日：2013-06-18

申请号：US12846162

申请日：2010-07-29

Applicant: Yosuke Shimamune ,  Akira Katakami ,  Akiyoshi Hatada ,  Masashi Shima ,  Naoyoshi Tamura

Inventor： Yosuke Shimamune ,  Akira Katakami ,  Akiyoshi Hatada ,  Masashi Shima ,  Naoyoshi Tamura

IPC: H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28518 ,  H01L21/30608 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  Y10S257/90

Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.

公开(公告)号：US20110254089A1

公开(公告)日：2011-10-20

申请号：US13169518

申请日：2011-06-27

Applicant: Hideomi SUZAWA ,  Yasuhiko TAKEMURA

Inventor： Hideomi SUZAWA ,  Yasuhiko TAKEMURA

IPC: H01L27/092

CPC classification number: H01L29/78636 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  Y10S257/90

Abstract: A semiconductor integrated circuit comprising thin-film transistors in each of which the second wiring is prevented from breaking at steps. A silicon nitride film is formed on gate electrodes and on gate wiring extending from the gate electrodes. Substantially triangular regions are formed out of an insulator over side surfaces of the gate electrodes and of the gate wiring. The presence of these substantially triangular side walls make milder the steps at which the second wiring goes over the gate wiring. This suppresses breakage of the second wiring.

Abstract translation: 一种包括薄膜晶体管的半导体集成电路，其中每个薄膜晶体管中的第二布线都被防止在步骤中断开。 在栅电极和从栅电极延伸的栅极布线上形成氮化硅膜。 在栅极电极和栅极布线的侧表面上形成由绝缘体构成的基本上三角形的区域。 这些基本上三角形的侧壁的存在使得第二布线越过栅极布线的步骤变得更加温和。 这抑制了第二布线的破损。