公开(公告)号：US20230245919A1

公开(公告)日：2023-08-03

申请号：US17588091

申请日：2022-01-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Francis Arendt ,  Damien Thomas Gilmore

IPC: H01L21/762 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L21/76221 ,  H01L21/28211 ,  H01L21/0217 ,  H01L21/02271

Abstract: Described examples include a method having steps of forming an isolation pad oxide layer on a substrate and forming and patterning a silicon nitride layer on the isolation pad oxide layer. The method also has steps of oxidizing portions of the substrate not covered by the silicon nitride layer to form a LOCOS layer and oxidizing the silicon nitride layer in an oxidizing ambient containing a chlorine source to form a silicon dioxide layer.

公开(公告)号：US09093531B2

公开(公告)日：2015-07-28

申请号：US13915441

申请日：2013-06-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hsien Chen ,  Tung Ying Lee ,  Yu-Lien Huang ,  Chi-Wen Liu

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76221 ,  H01L21/02233 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.

Abstract translation: 本发明涉及一种半导体器件的翅片结构。 用于半导体器件的示例性翅片结构包括从衬底的主表面突出的下部，其中所述下部包括具有第一晶格常数的第一半导体材料; 上部与下部具有界面，其中上部包括具有不同于第一晶格常数的第二晶格常数的第二半导体材料; 第一对凹口低于界面并延伸到下部的相对侧，其中每个第一凹口具有第一宽度; 以及延伸到界面的相对侧的第二对凹口，其中每个第二凹口具有大于第一宽度的第二宽度。

公开(公告)号：US08785290B2

公开(公告)日：2014-07-22

申请号：US13746532

申请日：2013-01-22

Applicant: Canon Kabushiki Kaisha

Inventor： Hiroaki Naruse

IPC: H01L21/76

CPC classification number: H01L21/76221 ,  H01L21/26586 ,  H01L29/0649

Abstract: A method for manufacturing a semiconductor device, the method comprising, forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern formed on the insulating layer as a mask, forming a first element isolation portion in the semiconductor substrate by implanting an ion into the semiconductor substrate using the photoresist pattern as a mask, forming a second element isolation portion, in the semiconductor substrate, whose outer edge is outside an outer edge of the opening, by implanting an ion into the semiconductor substrate through the opening, and forming a third element isolation portion, which is inside the outer edge of the second element isolation portion, by embedding an insulating member in the opening and removing the insulating layer.

Abstract translation: 一种制造半导体器件的方法，所述方法包括：使用形成在绝缘层上的光致抗蚀剂图案作为掩模在半导体衬底上形成绝缘层的开口，在半导体中形成第一元件隔离部分 通过使用光致抗蚀剂图案作为掩模将离子注入到半导体衬底中，在半导体衬底中形成第二元件隔离部分，该半导体衬底的外边缘位于开口的外边缘之外，通过将离子注入到半导体衬底中，通过 并且形成第三元件隔离部分，该第三元件隔离部分在第二元件隔离部分的外边缘内部，通过在开口中嵌入绝缘构件并去除绝缘层。

公开(公告)号：US20010039092A1

公开(公告)日：2001-11-08

申请号：US09846391

申请日：2001-05-02

Inventor： Hidenori Morimoto ,  Alberto O. Adan

IPC: H01L021/336

CPC classification number: H01L29/66613 ,  H01L21/76221 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/7835

Abstract: A semiconductor device comprises: gate electrode formed on a semiconductor substrate through the intervention of a gate insulating film; and a source/drain region provided with a silicide film on its surface and formed in the semiconductor substrate, wherein the source/drain region has an LDD region whose surface is partially or entirely tapered and an interface between the semiconductor substrate and the silicide film in the source/drain region is located higher than a surface of the semiconductor substrate below the gate electrode.

Abstract translation: 半导体器件包括：栅电极，通过栅极绝缘膜介入形成在半导体衬底上; 以及源极/漏极区域，在其表面上形成硅化物膜并形成在半导体衬底中，其中源极/漏极区域具有其表面部分或全部为锥形的LDD区域，以及半导体衬底和硅化物膜之间的界面 源极/漏极区域位于比栅极电极下方的半导体衬底的表面高的位置。

公开(公告)号：US06187640B1

公开(公告)日：2001-02-13

申请号：US09193252

申请日：1998-11-17

Applicant: Hiroyuki Shimada ,  Masaaki Higashitani ,  Hideo Kurihara ,  Hideki Komori ,  Satoshi Takahashi

Inventor： Hiroyuki Shimada ,  Masaaki Higashitani ,  Hideo Kurihara ,  Hideki Komori ,  Satoshi Takahashi

IPC: H01L21336

CPC classification number: H01L21/76221

Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below the first window is enhanced. Accordingly, generation of projection on bird's beak of a selective oxide film can be prevented in a semiconductor device manufacturing method including a step of growing a local oxidation of silicon film.

Abstract translation: 在制造半导体器件的方法中，包括在半导体衬底的表面上形成氧化防止层的步骤，在氧化防止层中形成第一窗口，将半导体衬底放置在第一气氛中，其中氧气 并且在第一温度下通过第一量的氯气供应第一量的氯气，然后在第一温度下加热第一选择性氧化物膜，以便通过热氧化从第一窗口露出的半导体衬底的表面生长第一选择性氧化物膜，形成第二窗口 通过图案化氧化防止层，并且将半导体衬底放置在第二气氛中，在第二气氛中，将氧气和大于第一量的第二量的氯气供给到第二气氛中，然后再次加热半导体衬底 温度使得形成第二选择性氧化物膜，并且第一选择性氧化物膜的厚度 在第一窗口下方形成的底片增强。 因此，在包括生长硅膜的局部氧化的步骤的半导体器件制造方法中，可以防止在选择性氧化物膜的鸟嘴上产生投影。

公开(公告)号：US6107145A

公开(公告)日：2000-08-22

申请号：US79901

申请日：1998-05-15

Applicant: Charles H. Dennison ,  Aftab Ahmad

Inventor： Charles H. Dennison ,  Aftab Ahmad

IPC: H01L21/336 ,  H01L21/60 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76897 ,  H01L21/76221 ,  H01L29/6656 ,  H01L29/66575 ,  Y10S438/975

Abstract: A method for forming a field effect transistor on a substrate includes providing a wordline on the substrate; providing composite masking spacers laterally outward relative to the wordline, the composite masking spacers comprising at least two different materials; removing at least one of the materials of the composite masking spacers to effectively expose the substrate area adjacent to the wordline for conductivity enhancing doping; and subjecting the effectively exposed substrate to conductivity enhancing doping to form source/drain regions. Another aspect of the invention is to provide a method for forming a field effect transistor including providing a gate on the substrate, providing a first layer of nitride over the gate; providing a second layer of a masking material over the first layer of nitride; anisotropically etching the first and second layers to define composite oxidation masking spacers positioned laterally outward relative to the patterned gate; and exposing the substrate to oxidation condition effective to form a field oxide region laterally outward of the composite oxidation masking spacers, the composite oxidation masking spacers effectively restricting oxidation of the substrate therebeneath.

Abstract translation: 在衬底上形成场效应晶体管的方法包括在衬底上提供字线; 提供相对于所述字线横向向外的复合掩模间隔物，所述复合掩模间隔物包括至少两种不同的材料; 去除所述复合掩模间隔物的至少一种材料以有效地暴露与所述字线相邻的衬底区域以进行导电性增强掺杂; 以及对有效暴露的衬底进行电导率增强掺杂以形成源极/漏极区域。 本发明的另一方面是提供一种用于形成场效应晶体管的方法，包括在衬底上提供栅极，在栅极上提供第一层氮化物; 在所述第一氮化物层上提供掩蔽材料的第二层; 各向异性地蚀刻第一层和第二层以限定相对于图案化的浇口横向向外定位的复合氧化掩模间隔物; 以及将所述衬底暴露于有效地形成所述复合氧化掩模间隔物的横向外部的场氧化物区域的氧化条件，所述复合氧化掩蔽间隔物有效地限制了其下的衬底的氧化。

公开(公告)号：US6103020A

公开(公告)日：2000-08-15

申请号：US971870

申请日：1997-11-19

Applicant: Ceredig Roberts ,  Werner Juengling

Inventor： Ceredig Roberts ,  Werner Juengling

IPC: H01L21/32 ,  H01L21/762 ,  H01L29/12

CPC classification number: H01L21/32 ,  H01L21/76221

Abstract: A field isolation process utilizes two or more isolation formation steps to form active areas on a semiconductor substrate. Each field isolation step forms a portion of the field isolation in a manner which reduces field oxide encroachment, in particular, by forming field oxide islands. The superposition of field isolation configurations define the desired active areas. A presently preferred dual-mask process may be carried out using a single masking stack, or more preferably using a masking stack for each isolation mask. The present isolation process further allows isolation features to be optimized for a variety of isolation requirements on the same integrated circuit.

Abstract translation: 场隔离过程利用两个或更多个隔离形成步骤在半导体衬底上形成有源区。 每个场隔离步骤以减少场氧化物侵蚀的方式形成场隔离的一部分，特别是通过形成场氧化物岛。 现场隔离配置的叠加定义了所需的有效区域。 目前优选的双掩模方法可以使用单个掩蔽叠层进行，或者更优选地使用用于每个隔离掩模的掩蔽堆叠。 本隔离过程进一步允许针对同一集成电路上的各种隔离要求进行优化的隔离特性。

公开(公告)号：US6043135A

公开(公告)日：2000-03-28

申请号：US19442

申请日：1998-02-05

Applicant: Kenji Noda

Inventor： Kenji Noda

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76221 ,  H01L21/76232

Abstract: A trench isolation is formed in a silicon substrate for defining active areas assigned to circuit components, and has an upper surface lower than a gate oxide layer grown on the adjacent active area; when the trench isolation is formed, silicon oxide is removed from the periphery of the silicon substrate defining a trench, then the surface of the silicon substrate is oxidized so that the silicon oxide deeply penetrates from the periphery into the silicon substrate, and, thereafter, insulating material fills the secondary trench defined by the silicon oxide; even through a gate electrode is patterned over the trench isolation, a pattern image for the gate electrode is exactly transferred to a photo-resist layer extending over the trench isolation, and the deeply penetrated silicon oxide prevents the channel region from concentration of electric field, thereby preventing the field effect transistor from the kinks and the inverse narrow width effect.

Abstract translation: 在硅衬底中形成沟槽隔离，用于限定分配给电路部件的有源区，并且具有比在相邻有源区上生长的栅氧化层更低的上表面; 当形成沟槽隔离时，从限定沟槽的硅衬底的外围去除氧化硅，然后氧化硅衬底的表面，使得氧化硅从外围深入硅衬底，然后， 绝缘材料填充由氧化硅限定的二次沟槽; 即使通过栅极电极被图案化在沟槽隔离上，用于栅电极的图案图像被精确地转移到在沟槽隔离物上延伸的光致抗蚀剂层，并且深穿透的氧化硅防止沟道区域被电场的集中， 从而防止场效应晶体管的扭结和反向窄宽度效应。

公开(公告)号：US5880009A

公开(公告)日：1999-03-09

申请号：US812426

申请日：1997-03-06

Applicant: Lin-Song Wang

Inventor： Lin-Song Wang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76221

Abstract: A method for forming oxides on buried N.sup.+ -type regions in a memory cell fabrication process, suitable for forming oxides on the bury N.sup.+ -type regions before self-aligned MOS device etching, comprises: (1) implanting a high concentration of impurity into the buried N.sup.+ -type regions; (2) annealing the chip; and (3) executing a dry oxide process and then a wet oxidation process to the chip, thereby preventing damage to the edges of buried N.sup.+ -type regions caused by non-uniform thickness of oxides on buried regions during self-aligned MOS etching and resolving the problem of non-uniform oxides on buried N.sup.+ -type regions.

Abstract translation: 在自对准MOS器件蚀刻之前，适用于在掩埋N +型区域上形成氧化物的存储单元制造工艺中在掩埋N +型区域上形成氧化物的方法包括：（1）将高浓度的杂质注入到 埋N +型区; （2）芯片退火; 和（3）对芯片执行干式氧化处理，然后进行湿式氧化处理，从而防止在自对准MOS蚀刻和分解过程中由掩埋区域上的氧化物的不均匀厚度引起的掩埋的N +型区域的边缘的损坏 埋藏N +型区域不均匀氧化物的问题。

公开(公告)号：US5696022A

公开(公告)日：1997-12-09

申请号：US632706

申请日：1996-04-15

Applicant: Se Aug Jang

Inventor： Se Aug Jang

IPC: H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/32 ,  H01L21/76221

Abstract: A method for forming a field oxide film for element isolation of a structure extending deeply in the substrate and having a step of small height, thereby exhibiting a low topology and a reduced bird's beak. The method includes the steps of forming a pattern of a mask material film for an oxidation prevention on a semiconductor substrate, locally forming an oxide film on a predetermined surface portion of the semiconductor substrate by use of an oxidation using the pattern as a mask, and removing the oxide film, thereby etching the predetermined surface portion of the semiconductor substrate while forming an undercut at a region defined beneath a side wall of the mask material film pattern, forming a lateral oxidation prevention film on the undercut disposed beneath the side wall of the mask material film pattern, and forming an oxide film for an element isolation, by use of an oxidation, on a portion of the semiconductor substrate exposed upon etching the predetermined surface portion of the semiconductor substrate.

Abstract translation: 一种用于形成用于元件隔离的场氧化膜的方法，所述场效应晶体深度延伸到所述衬底中并且具有小高度的步骤，从而表现出低拓扑结构和减少的鸟喙。 该方法包括以下步骤：在半导体衬底上形成用于氧化防止的掩模材料膜的图案，通过使用该图案作为掩模在氧化膜上局部形成半导体衬底的预定表面部分上的氧化膜;以及 去除氧化膜，从而在掩模材料膜图案的侧壁下方限定的区域形成底切，同时蚀刻半导体衬底的预定表面部分，在设置在掩模材料膜图案的侧壁下方的底切上形成侧面防氧化膜 掩模材料膜图案，并且通过使用氧化在用于蚀刻半导体衬底的预定表面部分的暴露的半导体衬底的一部分上形成用于元件隔离的氧化膜。