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公开(公告)号：US20120287726A1
公开(公告)日：2012-11-15
申请号：US13561248
申请日：2012-07-30
IPC分类号： G11C7/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译： 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。
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公开(公告)号：USRE43665E1
公开(公告)日：2012-09-18
申请号：US13268049
申请日：2011-10-07
IPC分类号： G11C16/00
CPC分类号： G11C16/3418
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.
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公开(公告)号：US08130542B2
公开(公告)日：2012-03-06
申请号：US12701085
申请日：2010-02-05
IPC分类号： G11C16/00
CPC分类号： G11C16/3418
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored in a first cell of a first word line, performing a read operation on an adjacent cell of a second word line in response to the request, determining whether the first cell is in a disturbed condition based on the read operation. The method includes reading data stored in the first cell in response to the read request by applying a read reference voltage to the first word line and adjusting a sensing parameter if the first cell is in the disturbed condition.
摘要翻译： 本公开的实施例提供用于读取非易失性多级存储器单元的方法，设备，模块和系统。 一种方法包括接收读取存储在第一字线的第一单元中的数据的请求，响应于该请求对第二字线的相邻单元执行读取操作，确定第一单元是否处于基于干扰状态 对读操作。 该方法包括：如果第一单元处于干扰状态，则通过将读取参考电压施加到第一字线并调整感测参数来读取响应于读取请求而存储在第一单元中的数据。
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24.发明授权Methods and apparatus for programming a memory cell using one or more blocking memory cells 有权使用一个或多个阻塞存储器单元编程存储器单元的方法和装置公开(公告)号：US08045386B2
公开(公告)日：2011-10-25
申请号：US12820430
申请日：2010-06-22
申请人： Giovanni Santin , Michele Incarnati
发明人： Giovanni Santin , Michele Incarnati
IPC分类号： G11C11/34
CPC分类号： G11C16/3418
摘要： Methods and apparatus for programming a memory cell using one or more blocking memory cells facilitate mitigation of capacitive voltage coupling. The methods include applying a program voltage to a selected memory cell of a string of memory cells, and applying a cutoff voltage to a set of one or more memory cells of the string between the selected memory cell and a select gate. The methods further include applying a pass voltage to one or more other memory cells of the string between the selected memory cell and the select gate. Other methods further include applying other pass voltages, other cutoff voltages and/or intermediate voltages to still other memory cells of the string.
摘要翻译： 使用一个或多个阻塞存储器单元来编程存储器单元的方法和装置有助于缓解电容性电压耦合。 所述方法包括将程序电压施加到存储器单元串的所选择的存储单元，以及将所述截止电压施加到所选存储单元和选择栅极之间的所述串的一个或多个存储单元的集合。 所述方法还包括将通过电压施加到所选择的存储器单元和选择栅极之间的串的一个或多个其它存储单元。 其他方法还包括将其他通过电压，其它截止电压和/或中间电压应用于串的其他存储单元。
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公开(公告)号：US07995395B2
公开(公告)日：2011-08-09
申请号：US12795764
申请日：2010-06-08
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译： 所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。 在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。 对所选存储单元执行另一个程序验证操作。 如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。 然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。
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公开(公告)号：US07911865B2
公开(公告)日：2011-03-22
申请号：US12613114
申请日：2009-11-05
申请人： Michele Incarnati , Giovanni Santin
发明人： Michele Incarnati , Giovanni Santin
IPC分类号： G11C7/04
摘要： A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates a multiple bit digital representation of an operational voltage and a multiple bit digital representation of a timing signal, both being functions of the integrated circuit temperature. A voltage generator converts the digital representation of the operational voltage to an analog voltage that biases portions of the integrated circuit requiring temperature compensated voltages. In one embodiment, the temperature compensated voltages bias memory cells. A timing generator converts the multiple bit digital representation of the timing signal to a logic signal.
摘要翻译： 温度传感器产生集成电路的温度的数字表示。 逻辑电路读取数字温度并产生作为集成电路温度的函数的定时信号的工作电压和多位数字表示的多位数字表示。 电压发生器将操作电压的数字表示转换为模拟电压，该模拟电压偏置需要温度补偿电压的集成电路的部分。 在一个实施例中，温度补偿电压偏置存储器单元。 定时发生器将定时信号的多位数字表示转换为逻辑信号。
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公开(公告)号：US07742338B2
公开(公告)日：2010-06-22
申请号：US11973733
申请日：2007-10-10
申请人： Giovanni Santin , Michele Incarnati
发明人： Giovanni Santin , Michele Incarnati
IPC分类号： G11C11/34
CPC分类号： G11C16/3418
摘要： A NAND architecture non-volatile memory device and programming process is described that reduces the effects of word line to word line voltage coupling by utilizing sets of two or more adjacent word lines and applying the same voltage to each in array access operations. This allows each word line of the set or pair to shield the other from word line to word line capacitive voltage coupling. In NAND memory string embodiments the various cells of strings of non-volatile memory cells are programmed utilizing modified or unmodified drain-side self boost, source-side self boost, local self boost, and virtual ground programming processes that utilize two or more “blocking” memory cells on either the source line side and drain line side of a selected memory cell. The paired blocking cells shield each other during programming to reduce coupled noise, to prevent charge leakage from the boosted channel of the selected memory cell.
摘要翻译： 描述了NAND架构非易失性存储器件和编程过程，其通过利用两个或更多个相邻字线的集合并将阵列访问操作中的每一个施加相同的电压来减少字线对字线电压耦合的影响。 这允许集合或对的每个字线将另一个字符从字线屏蔽到字线电容电压耦合。 在NAND存储器串实施例中，使用经修改或未修改的漏极侧自增强，源侧自增强，局部自增强和使用两个或多个“阻塞”的虚拟地面编程过程来编程非易失性存储器单元串的各个单元 “存储单元位于所选存储单元的源极线侧和漏极线侧上。 配对的阻塞单元在编程期间相互屏蔽以减少耦合噪声，以防止来自所选存储单元的升压通道的电荷泄漏。
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公开(公告)号：US20100091582A1
公开(公告)日：2010-04-15
申请号：US12365589
申请日：2009-02-04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译： 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。
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29.发明授权Single latch data circuit in a multiple level cell non-volatile memory device 有权单级锁存数据电路在多级单元非易失性存储器件中公开(公告)号：US07417894B2
公开(公告)日：2008-08-26
申请号：US11506428
申请日：2006-08-18
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C11/34
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译： 单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。 该电路由具有反向节点和非反相节点的锁存器组成。 第一控制晶体管选择性地将非反相节点耦合到锁存器输出。 第二控制晶体管选择性地将反相节点耦合到锁存器输出。 复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。
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公开(公告)号：US07324383B2
公开(公告)日：2008-01-29
申请号：US11414982
申请日：2006-05-01
申请人： Michele Incarnati , Giovanni Santin , Tommaso Vali
发明人： Michele Incarnati , Giovanni Santin , Tommaso Vali
IPC分类号： G11C16/06
CPC分类号： G11C16/3404
摘要： A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.
摘要翻译： 多个存储器单元被编程，其中增加的编程脉冲被施加到存储器单元耦合到的字线。 在每个脉冲之后，验证操作确定每个单元的阈值电压。 当阈值电压达到预验证阈值时，只有连接到该特定单元的位线被中间电压偏置，该中间电压降低了单元的Vcc变化。 其他细胞继续按其正常速度进行编程。 由于每个单元的V OUT达到预验证电平，所以它被中间电压偏置。 当它们的阈值电压达到验证电压阈值时，所有位线都被抑制电压偏置。
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