SIGNAL CALIBRATION METHOD, AND DEVICE GENERATED BASED ON IMBALANCE OF I PATH AND Q PATH, AND STORAGE MEDIUM

    公开(公告)号:US20200373964A1

    公开(公告)日:2020-11-26

    申请号:US16959437

    申请日:2018-12-29

    IPC分类号: H04B1/7107 H04B1/04 H04B1/00

    摘要: The present disclosure provides a signal calibration method, apparatus and device generated based on an imbalance of I path and Q path. The method includes sending a cosine signal and a sine signal through a signal generator, transmitting the cosine signal and the sine signal in the I path and the Q path respectively, the cosine signal and the sine signal being configured to loop back to a signal receiving direction after passing through a transmitting amplifier; processing a signal obtained by a down converter in the signal receiving direction; performing a phase adjustment and an amplitude adjustment by adjusting the signal generator, gain amplifiers of I path and Q path analog domains, and a corresponding digital domain, so as to determine an appropriate phase cancellation value and an appropriate amplitude cancellation value for an image signal; and calibrating the image signal corresponding to the signal to be calibrated.

    Dual-Edge Triggered Ring Buffer And Communication System

    公开(公告)号:US20200278944A1

    公开(公告)日:2020-09-03

    申请号:US16759626

    申请日:2018-11-13

    IPC分类号: G06F13/40 G06F13/42 G06F11/16

    摘要: The present disclosure provides a dual-edge triggered ring buffer and a communication system. The dual-edge triggered ring buffer includes a logic clock generation module and a data writing module. The logic clock generation module is configured to generate a corresponding first logic clock signal upon detecting an input of the trigger signal corresponding to the multiple first trigger signal input terminals, or to generate a corresponding second logic clock signal upon detecting an input of the trigger signal corresponding to the multiple second trigger signal input terminals. The data writing module is configured to write data output from the external system through the multiple corresponding input terminals according to the first logic clock signal or the second logic clock signal.