-
21.发明申请Method, System, and Computer Program Product for Dynamically Selecting Software Buffers for Aggregation According to Current System Characteristics 失效根据当前系统特性动态选择软件缓冲区进行聚合的方法，系统和计算机程序产品公开(公告)号：US20090031059A1
公开(公告)日：2009-01-29
申请号：US12253770
申请日：2008-10-17
IPC分类号： G06F13/10
CPC分类号： G06F9/5016 , G06F2209/5011
摘要： A method, system, and computer program product in a data processing system are disclosed for dynamically selecting software butters for aggregation in order to optimize system performance. Data to be transferred to a device is received. The data is stored in a chain of software buffers. Current characteristics of the system are determined. Software buffers to be combined are then dynamically selected. This selection is made according to the characteristics of the system in order to maximize performance of the system.
摘要翻译： 公开了一种数据处理系统中的方法，系统和计算机程序产品，用于动态选择用于聚合的软件，以优化系统性能。 接收要传输到设备的数据。 数据存储在软件缓冲区链中。 确定系统的当前特性。 然后动态选择要组合的软件缓冲区。 该选择是根据系统的特性进行的，以便最大限度地提高系统性能。
-
22.发明申请公开(公告)号：US20080232349A1
公开(公告)日：2008-09-25
申请号：US12131367
申请日：2008-06-02
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/283
摘要： Method, system and computer program product for transferring data in a data processing system network. A method for transferring data in a data processing system network according to the invention includes determining an adapter among a plurality of adapters that has the lowest transmit latency, and assigning data to be transferred to the adapter determined to have the lowest transmit latency. The data to be transferred is then transferred by the assigned adapter. The present invention utilizes network adapters to transfer data in a more efficient manner.
摘要翻译： 用于在数据处理系统网络中传输数据的方法，系统和计算机程序产品。 根据本发明的用于在数据处理系统网络中传送数据的方法包括：确定具有最低发射延迟的多个适配器之间的适配器，以及将要传送到适配器的数据分配给确定具有最低发射延迟的适配器。 要转让的数据然后由分配的适配器传输。 本发明利用网络适配器以更有效的方式传输数据。
-
23.发明申请END-TO-END DATA INTEGRITY PROTECTION FOR PCI-EXPRESS BASED INPUT/OUTPUT ADAPTER 审中-公开基于PCI-EXPRESS的输入/输出适配器的端到端数据完整性保护公开(公告)号：US20080133981A1
公开(公告)日：2008-06-05
申请号：US11940453
申请日：2007-11-15
IPC分类号： G06F11/00
CPC分类号： H03M13/09 , H04L1/004 , H04L1/0061 , H04L2001/0094
摘要： Method, system and computer program product for protecting the integrity of data transferred between an input/output bus of a data processing system and an external network. A method for protecting the integrity of data transferred between an input/output bus and a network includes generating a Cyclic Redundancy Check (CRC) value on an interface between the input/output bus and an adapter for data being transferred from the input/output bus to the network, and checking a CRC value on the interface between the input/output bus and the adapter for data being transferred from the network to the input/output bus. By adding a CRC generator and a CRC checker on the interface between the input/output bus and the adapter, end-to-end data integrity protection is provided for data transferred between the input/output bus and the network.
摘要翻译： 用于保护在数据处理系统的输入/输出总线与外部网络之间传送的数据完整性的方法，系统和计算机程序产品。 一种用于保护在输入/输出总线和网络之间传输的数据的完整性的方法包括在输入/输出总线与适配器之间的接口上产生循环冗余校验（CRC）值，以便从输入/输出总线 并且检查输入/输出总线和适配器之间的接口上的CRC值，以便数据从网络传输到输入/输出总线。 通过在输入/输出总线和适配器之间的接口上添加CRC生成器和CRC校验器，为输入/输出总线和网络之间传输的数据提供端到端的数据完整性保护。
-
24.发明授权Method and apparatus for transferring data from a memory subsystem to a network adapter for improving the memory subsystem and PCI bus efficiency 有权用于将数据从存储器子系统传送到网络适配器以用于改善存储器子系统和PCI总线效率的方法和装置公开(公告)号：US07356664B2
公开(公告)日：2008-04-08
申请号：US10621931
申请日：2003-07-17
IPC分类号： G06F12/00
CPC分类号： G06F12/04
摘要： A method, apparatus, and computer instructions for transferring data from a memory to a network adapter. A request is received to transfer data to a network adapter. An offset is set for a starting address of the data to align the data with an end of a frame in the memory, wherein the frame is transferred from the memory to the network adapter.
摘要翻译： 一种用于将数据从存储器传送到网络适配器的方法，装置和计算机指令。 接收到将数据传送到网络适配器的请求。 为数据的起始地址设置偏移量以将数据与存储器中的帧的结尾对准，其中帧从存储器传送到网络适配器。
-
25.发明授权Programmable unit for controlling and interfacing of I/O busses of dissimilar data processing systems 失效用于控制和接口不同数据处理系统的I / O总线的可编程单元
公开(公告)号：US5581741A
公开(公告)日：1996-12-03
申请号：US341848
申请日：1994-11-16
CPC分类号： G06F13/4027
摘要： A programmable I/O bus adapter for interfacing and controlling two data processing systems having dissimilar and incompatible architectures. The programmable I/O bus adapter is capable of controlling the I/O bus and adapters of each of the two data processing systems. Simultaneously, the I/O bus adapter provides for interfacing and communication between the two dissimilar data processing systems. Interfacing from the bus adapter to each data processing system is provided by circuitry provided on integrated circuit chip sets specifically designed to interface with each system. The interfacing circuitry is enabled to convert signals between each system to allow for communication. Communication paths couple the adapter to the I/O bus of each system. The ability to access and control an I/O bus and adapter of each system is provided by a microprocessor having microcode instructions stored in programmable memory. The microcode provides for self-contained operation of the I/O bus adapter by enabling it to independently perform I/O control functions of the coupled systems. The microprocessor may be implemented by using a RISC architecture microprocessor device.
摘要翻译： 一种可编程I / O总线适配器，用于连接和控制具有不相似和不兼容架构的两个数据处理系统。 可编程I / O总线适配器能够控制两个数据处理系统中的每一个的I / O总线和适配器。 同时，I / O总线适配器提供两个不同数据处理系统之间的接口和通信。 从总线适配器到每个数据处理系统的接口由专门设计成与每个系统接口的集成电路芯片组上提供的电路提供。 接口电路能够在每个系统之间转换信号以允许通信。 通信路径将适配器连接到每个系统的I / O总线。 访问和控制每个系统的I / O总线和适配器的能力由具有存储在可编程存储器中的微代码指令的微处理器提供。 微代码通过使其独立地执行耦合系统的I / O控制功能来提供I / O总线适配器的独立操作。 微处理器可以通过使用RISC架构微处理器设备来实现。
-
26.发明授权Performance enhancement for ANSI X3.92 data encryption algorithm standard 失效ANSI X3.92数据加密算法标准的性能提升
公开(公告)号：US5317638A
公开(公告)日：1994-05-31
申请号：US916777
申请日：1992-07-17
CPC分类号： H04L9/0625
摘要： ANSI X3.92 Data Encryption algorithm is public knowledge, and is widely used where data security and integrity is vital, such as commercial banks, secret service organizations etc. Even though this algorithm is feasible to implement in software, it is impractical to achieve desired performance for most of the applications. Hence, a hardware solution is highly recommended. Prior art DES hardware in CMOS technology served performance needs of low-end and mid-range systems only, due to the technology constraints. However, some of these constraints are removed through the technology breakthroughs and the current CMOS is well suited for high performance applications. While prior art DES designs allowed one round per cycle to minimize the cell count, the current technology allows of multiple rounds per cycle due to the denser CMOS chip technology. In order to maximize the number of rounds for a given cycle time, careful study of algorithm to determine the critical paths from a logic implementation perspective is required. This invention identifies one such path in f-function of the DES algorithm, where the expanded data and the key is XOR'd prior to entering S-function. It is mathematically proven that if the left half of the input data is expanded and XOR'ed with the second key at the same time the right half of the input data which is still going through its XOR, S-function, permute and expansion, then this expanded result can be immediately XOR'ed with the left input data being expanded and XOR'ed in parallel. The resulting output can be used as input to the next S-function, thus eliminating a stage of expansion and XOR logic for all subsequent S-function inputs in rounds 2 through 15.
摘要翻译： ANSI X3.92数据加密算法是公共知识，在数据安全和完整性至关重要的情况下被广泛使用，如商业银行，秘密服务机构等。即使这种算法在软件中实现是可行的，实现期望是不切实际的 大多数应用的性能。 因此，强烈建议使用硬件解决方案。 由于技术上的限制，现有技术的CMOS技术的DES硬件只能满足低端和中端系统的性能需求。 然而，通过技术突破，可以消除其中的一些限制，目前的CMOS非常适合高性能应用。 虽然现有技术的DES设计允许每个周期一个循环以使细胞计数最小化，但由于采用更密集的CMOS芯片技术，目前的技术允许每个周期多轮。 为了最大化给定循环时间的轮数，需要从逻辑实现的角度仔细研究确定关键路径的算法。 本发明在DES算法的f函数中识别一个这样的路径，其中扩展的数据和密钥在进入S函数之前是异或的。 在数学上证明，如果输入数据的左半部分在第二个键的同时被扩展并且与正在经历其XOR，S函数，置换和扩展的输入数据的右半部分相异， 那么这个扩展结果可以立即异或左输入数据被扩展并并行XOR。 所得到的输出可以用作下一个S函数的输入，从而消除了第2到15周期中所有后续S函数输入的扩展阶段和异或逻辑。
-
公开(公告)号：US20110167293A1
公开(公告)日：2011-07-07
申请号：US13050372
申请日：2011-03-17
IPC分类号： G06F11/20
CPC分类号： G06F11/2221 , G06F11/004 , G06F11/2017
摘要： A primary I/O adapter and a redundant I/O adapter of a data processing system are assigned to support access to a system resource. While the primary I/O adapter is in service and the redundant I/O adapter is not in service in providing access to the system resource, a fail over command is issued to remove the primary I/O adapter from service and place the redundant I/O adapter in service in supporting access to the system resource. While the redundant I/O adapter is in service and the primary I/O adapter is not in service in providing access to the system resource, diagnostic testing on the primary I/O adapter is performed. In response to the diagnostic testing revealing no fault in the primary I/O adapter, a fail back command is issued to restore the primary I/O adapter to service and to remove the redundant I/O adapter from service.
摘要翻译： 分配数据处理系统的主I / O适配器和冗余I / O适配器以支持对系统资源的访问。 当初级I / O适配器处于使用状态并且冗余I / O适配器未提供对系统资源的访问时，将发出故障转移命令以从服务中删除主I / O适配器，并将冗余I / / O适配器在服务中支持对系统资源的访问。 当冗余I / O适配器处于使用状态并且主I / O适配器未提供对系统资源的访问时，将执行主I / O适配器的诊断测试。 响应诊断测试显示主I / O适配器无故障，将发出故障恢复命令以恢复主要I / O适配器的服务，并从服务中删除冗余I / O适配器。
-
28.发明申请LARGE SEND SUPPORT IN LAYER 2 SWITCH TO ENHANCE EFFECTIVENESS OF LARGE RECEIVE ON NIC AND OVERALL NETWORK THROUGHPUT 有权大容量发送支持2层交换机，提高大容量接入网卡和整体网络的有效性公开(公告)号：US20100260186A1
公开(公告)日：2010-10-14
申请号：US12421731
申请日：2009-04-10
申请人： Binh K. Hua , Sivarama K. Kodukula
发明人： Binh K. Hua , Sivarama K. Kodukula
IPC分类号： H04L12/56
CPC分类号： H04L49/10
摘要： The present disclosure is directed to a method for delivering a plurality of packets from a network switch to a receiving node. The method may comprise collecting a plurality of packets received at the network switch during a time window; arranging the plurality of packets based on a source address, a package number, and a destination address for each one of the plurality of packets collected during the time window; and delivering the arranged plurality of packets to the receiving node.
摘要翻译： 本公开涉及一种用于将多个分组从网络交换机递送到接收节点的方法。 该方法可以包括在时间窗口期间收集在网络交换机处接收的多个分组; 基于在时间窗口期间收集的多个分组中的每个分组的源地址，包编号和目的地地址来排列多个分组; 以及将所排列的多个分组递送到所述接收节点。
-
29.发明授权Method and apparatus for managing flow control in a data processing system 失效一种用于管理数据处理系统中流量控制的方法和装置公开(公告)号：US07796509B2
公开(公告)日：2010-09-14
申请号：US12371793
申请日：2009-02-16
IPC分类号： H04L12/26
摘要： A method in a data processing system for managing transmission of pause frames. In response to detecting an overflow condition during a receipt of data from a network, enabling flow control in response to detecting the overflow condition. The flow control is enabled as long as the overflow condition is present. A determination is made as to whether the operating system unavailable after a period of time passes. If the operating system believed to have crashed and flow control is enabled, the flow control is disabled.
摘要翻译： 一种用于管理暂停帧的传输的数据处理系统中的方法。 响应于在从网络接收数据期间检测到溢出情况，响应于检测到溢出状况而启用流量控制。 只要存在溢出条件，就启用流量控制。 在经过一段时间后，确定操作系统是否不可用。 如果操作系统相信已经崩溃并启用了流量控制，则流量控制将被禁用。
-
公开(公告)号：US07765290B2
公开(公告)日：2010-07-27
申请号：US12130808
申请日：2008-05-30
申请人： Binh K. Hua , Sivarama K. Kodukula
发明人： Binh K. Hua , Sivarama K. Kodukula
IPC分类号： G06F15/173
CPC分类号： H04L45/00 , H04L45/245 , H04L45/28 , Y02D50/30
摘要： Methods and arrangements to monitor communication components such as a network adapters for activity, and identify components that have lower than normal levels of activity are provided. An identified communication component can become suspect component and a candidate for further testing, including different forms of interrogation. Process for interrogating candidates can include generating and sending test packets having the media access control (MAC) address of the candidate to the candidate and if activity is not detected subsequent to the interrogation, the candidate can be flagged as a failed component. Correspondingly, the component can be deactivated and removed from service. In a further embodiment, a backup component can be activated and assume the role previously held by the failed component.
-
-
-
-
-
-
-
-
-
搜索结果
37 条记录 (耗时 0.013 秒)
