公开(公告)号：US5946242A

公开(公告)日：1999-08-31

申请号：US883537

申请日：1997-06-26

Applicant: Soo-In Cho ,  Sang-Jae Rhee

Inventor： Soo-In Cho ,  Sang-Jae Rhee

IPC: G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C29/06 ,  G11C29/50 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C29/50 ,  G11C11/401

Abstract: A circuit for generating an internal source voltage signal responsive to an external source voltage signal in a semiconductor memory device prevents malfunction and extends the lifetime of the device by clamping the internal source signal if the device is in a normal operating mode when the external source signal is in a stress operating range. When the device is placed in a test mode, the circuit allows the internal source signal to increase in proportion to the level of the external source signal when the external source signal is in a stress operating range. The circuit includes in internal source voltage generator, which always clamps the internal source signal when the external source signal is in a normal operating range, and a pull-up unit which is activated in response to a control signal. The control signal is enabled when the device is placed in a test mode by combining external timing signals.

Abstract translation: 用于在半导体存储器件中产生响应于外部源极电压信号的内部源极电压信号的电路防止故障，并且如果器件处于正常工作模式时通过钳位内部源极信号来延长器件的寿命，当外部源极信号 处于压力操作范围。 当器件处于测试模式时，当外部源极信号处于应力工作范围时，该电路允许内部源极信号与外部源极信号的电平成正比。 该电路包括内部源电压发生器，当外部源极信号处于正常工作范围时，它始终夹紧内部源极信号，以及响应控制信号激活的上拉单元。 当通过组合外部定时信号将器件置于测试模式时，控制信号被使能。

公开(公告)号：US5748543A

公开(公告)日：1998-05-05

申请号：US705556

申请日：1996-08-29

Applicant: Sang-Bo Lee ,  Soo-In Cho

Inventor： Sang-Bo Lee ,  Soo-In Cho

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/72 ,  G11C29/785

Abstract: Self repairing integrated circuit memory devices include the plurality of normal memory cells, plurality of spare memory cells and a plurality of spare substituting circuits. A spare substituting circuit is responsive to a defective normal memory cell address which is programmed therein, to substitute at least one spare memory cell for at least one defective normal memory cell which is located at the defective normal memory cell address which is programmed therein. A sequential spare substituting circuit selector is connected to the spare substituting circuits and is responsive to a defect indication signal, to sequentially select a respective one of the spare circuits for programming with sequential ones of the defective normal memory cell addresses. An alarm signal is generated if all of the spare substituting circuits have been used. If a defect is present in at least two normal memory cells in different rows and the same column, a spare column is substituted rather than two spare rows. Also, if all rows substituting circuits have been programmed spare column substituting circuits are used. Defective addresses are programmed using electrically programmable fuses preferably polycrystalline silicon elongated fuses.

Abstract translation: 自修复集成电路存储器件包括多个正常存储器单元，多个备用存储单元和多个备用替换电路。 备用替代电路响应于其中编程的有缺陷的正常存储器单元地址，以替代至少一个备用存储器单元，该至少一个故障正常存储器单元位于其中编程的故障正常存储器单元地址。 顺序的备用电路选择器连接到备用替代电路，并且响应于缺陷指示信号，顺序地选择备用电路中的相应一个，以用有序的正常存储器单元地址中的顺序选择。 如果已经使用所有备用替换电路，则产生报警信号。 如果在不同行和相同列中的至少两个正常存储单元中存在缺陷，则替换备用列而不是两个备用行。 而且，如果所有行代替电路都被编程，则使用备用列替代电路。 使用电可编程保险丝，优选多晶硅细长型保险丝来编程不良地址。

公开(公告)号：US5629894A

公开(公告)日：1997-05-13

申请号：US563407

申请日：1995-11-30

Applicant: Soo-In Cho ,  Dong-Il Seo ,  Seung-Moon Yoo

Inventor： Soo-In Cho ,  Dong-Il Seo ,  Seung-Moon Yoo

IPC: G11C11/413 ,  G06F11/10 ,  G11C7/00 ,  G11C11/401 ,  G11C16/06 ,  G11C13/00

CPC classification number: G06F11/1056 ,  G11C7/00

Abstract: A memory module having parity and capable of performing a read-modify-write (RMW) operation is provided. The memory module has data input and output pins for processing a plurality of data bits and a parity bit and is comprised of one semiconductor memory device which processes the parity bit and a plurality of semiconductor memory devices which each process a plurality of data bits. All of the memory devices include at least one data input/output pin for receiving and supplying data and at least one control pin for receiving a control signal. The memory module according to the present invention is simply constructed so as to yield high integration in a semiconductor integrated circuit, and is capable of high-speed applications.

Abstract translation: 提供具有奇偶校验并且能够执行读 - 修改 - 写（RMW）操作的存储器模块。 存储器模块具有用于处理多个数据位和奇偶校验位的数据输入和输出引脚，并且包括处理奇偶校验位的一个半导体存储器件以及处理多个数据位的多个半导体存储器件。 所有存储器件包括用于接收和提供数据的至少一个数据输入/输出引脚和用于接收控制信号的至少一个控制引脚。 根据本发明的存储器模块简单地构造成在半导体集成电路中产生高集成度，并且能够高速应用。

公开(公告)号：US4920280A

公开(公告)日：1990-04-24

申请号：US187930

申请日：1988-04-29

Applicant: Soo-In Cho ,  Dong-Sun Min

Inventor： Soo-In Cho ,  Dong-Sun Min

IPC: G11C11/413 ,  G05F3/20 ,  G11C5/14 ,  G11C11/408 ,  H02M3/158 ,  H03K5/08

CPC classification number: H03K5/08 ,  G05F3/205 ,  G11C5/146 ,  H02M3/158 ,  H01L2924/0002

Abstract: A circuit for generating a back bias voltage for use in a semiconductor memory device is disclosed, wherein the back bias voltage is clamped within a desired voltage level. The circuit comprises an oscillator for generating a sequence of square waves having a specified frequency, a buffer adapted to be connected with the output of said oscillator and for buffering the output of said oscillator into the square waves having a level of a source supply voltage, a charge pump circuit for providing a back bias voltage by receiving the output of said buffer, and a clamping circuit adapted to be coupled in parallel between the output of said charge pump circuit and a ground level and for clamping within a specified range the back bias voltage being provided by said charge pump circuit in accordance with variations of said source supply voltage.

Abstract translation: 公开了一种用于产生用于半导体存储器件的背偏压的电路，其中将背偏压钳位在期望的电压电平之内。 该电路包括用于产生具有指定频率的方波序列的振荡器，适于与所述振荡器的输出连接的缓冲器，用于将所述振荡器的输出缓冲为具有源电源电压电平的方波， 用于通过接收所述缓冲器的输出来提供反向偏置电压的电荷泵电路，以及适于在所述电荷泵电路的输出与地电平之间并联耦合并用于在指定范围内钳位的钳位电路 电压由所述电荷泵电路根据所述源电源电压的变化提供。