公开(公告)号：US06983010B1

公开(公告)日：2006-01-03

申请号：US09542042

申请日：2000-03-31

申请人： Jae-yoon Sim ,  Hong-joon Park ,  Soo-in Cho ,  Jung-bae Lee

发明人： Jae-yoon Sim ,  Hong-joon Park ,  Soo-in Cho ,  Jung-bae Lee

IPC分类号： H03H7/30

CPC分类号： G11C7/1057 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H01L27/088 ,  H04L27/01

摘要： A high frequency equalizer using a demultiplexing technique and a semiconductor device using the same are provided. The high frequency equalizer demultiplexes input data input through an input and output terminal into a plurality of input data items, each having a time difference that is the same as the period of the input data. The equalizer restores the lost high frequency data components of the plurality of demultiplexed input data items, multiplexes the restored plurality of data items, and sequentially outputs the restored data items one by one. Therefore, using this high frequency equalizer, it is possible to allow enough time to restore the lost high frequency component even though the period of the input data is reduced by an increase of the data transmission speed. Using this high frequency equalizer, it is possible to correctly restore the lost high frequency component even at a high data transmission speed. Therefore, according to the semiconductor device including the high frequency equalizer, the lost high frequency component of data can be restored even at a high data transmission speed.

摘要翻译： 提供了使用解复用技术的高频均衡器和使用其的半导体器件。 高频均衡器将通过输入和输出端输入的输入数据解复用为多个输入数据项，每个具有与输入数据周期相同的时间差。 均衡器恢复多路复用输入数据项的丢失的高频数据分量，复用恢复的多个数据项，并逐个依次输出恢复的数据项。 因此，即使通过数据传输速度的增加来减少输入数据的周期，也可以使用这种高频均衡器来允许足够的时间来恢复丢失的高频分量。 使用该高频均衡器，即使在高数据传输速度下也可以正确地恢复丢失的高频分量。 因此，根据包括高频均衡器的半导体器件，即使在高数据传输速度下也可以恢复数据的丢失高频分量。

公开(公告)号：US20050114064A1

公开(公告)日：2005-05-26

申请号：US10911503

申请日：2004-08-05

申请人： Joo-weon Shin ,  Byung-chul Kim ,  Seung-bum Ko ,  Soo-in Cho

发明人： Joo-weon Shin ,  Byung-chul Kim ,  Seung-bum Ko ,  Soo-in Cho

IPC分类号： G11C29/00 ,  G01D3/00 ,  G11C29/34

CPC分类号： G11C29/34 ,  G11C2029/2602

摘要： A method for performing a parallel bit test of a semiconductor memory device, including writing data to each of a plurality of memory cells, reading data from each of the plurality of memory cells, testing the data from each of the plurality of memory cells in a first test mode, and testing the data from each of the plurality of memory cells in a second test mode. A circuit including a first test mode circuit for receiving first data, a second test mode circuit for receiving second data, and wherein the first test mode circuit tests the received first data and the second test mode tests the received second data. Another circuit including a first comparator with a plurality of comparison circuits, a test mode selector for selecting at least one of a plurality of outputs from the first comparator, and a second comparator for receiving the selected output.

摘要翻译： 一种用于执行半导体存储器件的并行位测试的方法，包括将数据写入多个存储器单元中的每一个，从多个存储器单元中的每一个读取数据，在多个存储单元中的每一个存储单元中测试数据 第一测试模式，并且在第二测试模式中测试来自多个存储器单元中的每一个的数据。 一种电路，包括用于接收第一数据的第一测试模式电路，用于接收第二数据的第二测试模式电路，并且其中第一测试模式电路测试接收的第一数据，第二测试模式测试接收的第二数据。 另一个电路包括具有多个比较电路的第一比较器，用于选择来自第一比较器的多个输出中的至少一个的测试模式选择器，以及用于接收所选输出的第二比较器。

公开(公告)号：US6094376A

公开(公告)日：2000-07-25

申请号：US998287

申请日：1997-12-24

申请人： Pil-Soon Park ,  Kyung-Woo Kang ,  Soo-In Cho

发明人： Pil-Soon Park ,  Kyung-Woo Kang ,  Soo-In Cho

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C16/04

CPC分类号： G11C7/1051

摘要： A data output buffer control circuit for a semiconductor memory device assures a column address setup time and a valid data setup time in EDO mode by eliminating short glitches in the data output buffer. The circuit assures the column address setup time by disabling the data output buffer for a predetermined period of time after an address transition, regardless of the state of a column address strobe signal. The circuit assures the setup time for valid data by sensing when the address is set up relative to when the column address strobe signal is activated, and then enabling the data output buffer so as to maintain invalid data in the data output buffer long enough to prevent a short glitch in the data output buffer if the column address is set up before the column address strobe signal is activated. The circuit includes a pulse generator for generating a pulse signal each time it senses a column address transition, and a latch circuit for combining the pulse signal with the column address strobe signal so as to generate a buffer control signal for enabling and disabling the data output buffer.

摘要翻译： 用于半导体存储器件的数据输出缓冲器控制电路通过消除数据输出缓冲器中的短毛刺来确保EDO模式下的列地址建立时间和有效的数据建立时间。 该电路通过在地址转换之后的预定时间段禁用数据输出缓冲器来确保列地址建立时间，而不管列地址选通信号的状态如何。 电路通过检测地址是否相对于列地址选通信号被激活而设置的时间来保证有效数据的建立时间，然后启用数据输出缓冲器，以便在数据输出缓冲器中保持足够长的时间以防止 如果在列地址选通信号被激活之前设置了列地址，则数据输出缓冲器中的短暂毛刺。 电路包括用于每次检测列地址转换时产生脉冲信号的脉冲发生器和用于将脉冲信号与列地址选通信号组合的锁存电路，以便产生用于启用和禁用数据输出的缓冲器控制信号 缓冲。

公开(公告)号：US5610869A

公开(公告)日：1997-03-11

申请号：US511815

申请日：1995-08-07

申请人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

发明人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

IPC分类号： G11C5/14 ,  H02M3/07 ,  G11C13/00

CPC分类号： H02M3/07 ,  G11C5/145

摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

摘要翻译： 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

公开(公告)号：US5130580A

公开(公告)日：1992-07-14

申请号：US550997

申请日：1990-07-11

申请人： Dong-sun Min ,  Hong-sun Hwang ,  Soo-in Cho ,  Dae-Je Chin

发明人： Dong-sun Min ,  Hong-sun Hwang ,  Soo-in Cho ,  Dae-Je Chin

IPC分类号： G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409

CPC分类号： G11C7/065

摘要： A sense amplifier driving circuit for controlling sense amplifiers of high density semiconductor memory device by turning-on/off a driving transistor connected between an external voltage Vcc terminal and a ground voltage Vss terminal, comprises a bias circuit including a MOS transistor being connected to the driving MOS transistor to form a current mirror circuit therewith which is controlled by a sense amplifier enable clock and a constant current source having a MOS transistor with a bias voltage of an intermediate level between Vcc and Vss being applied to its gate terminal. The bias circuit is connected to the gate terminal of the driving transistor to control the gate voltage of the driving transistor, thereby reducing the peak current of a sense amplifier driving signal. Further, the driving signals are generated in the waveform having a linear dual slope, resulting in a decrease in power-noise. The bias circuit is connected to a clamping circuit having a comparator circuit to clamp the active restore voltage of the sense amplifier driving circuit, so that the active restore voltage can be maintained at the level of an internal voltage (approximately 4V), thereby preventing the distortion of the characteristics of the cell device and eliminating the necessity of additional standby current by enabling the sense amplifier only for the active restore operation. Further, the sense amplifier driving circuit comprises a constant circuit including two or more current mirror circuits which are sequentially activated, whereby the sense amplifier driving signals are made to have stable linear dual slopes.

摘要翻译： 一种读出放大器驱动电路，用于通过接通/断开连接在外部电压Vcc端子和接地电压Vss端子之间的驱动晶体管来控制高密度半导体存储器件的读出放大器，包括：偏置电路，包括MOS晶体管，连接到 驱动MOS晶体管与其形成电流镜像电路，其由读出放大器使能时钟控制，并且具有MOS晶体管的恒定电流源，其中Vcc和Vss之间的中间电平的偏置电压被施加到其栅极端子。 偏置电路连接到驱动晶体管的栅极端子，以控制驱动晶体管的栅极电压，从而降低读出放大器驱动信号的峰值电流。 此外，在具有线性双斜率的波形中产生驱动信号，导致功率噪声的降低。 偏置电路连接到具有比较器电路的钳位电路，以钳位读出放大器驱动电路的有效恢复电压，使得有效恢复电压可以保持在内部电压（大约4V）的水平，从而防止 通过使感测放大器仅用于主动恢复操作，从而消除了电池装置特性的失真，并消除了额外待机电流的必要性。 此外，读出放大器驱动电路包括一个恒定电路，该恒定电路包括被依次激活的两个或多个电流镜电路，从而使读出放大器驱动信号具有稳定的线性双斜率。

公开(公告)号：US06266286B1

公开(公告)日：2001-07-24

申请号：US09457909

申请日：1999-12-08

申请人： Soo-In Cho ,  Jong-Hyun Choi

发明人： Soo-In Cho ,  Jong-Hyun Choi

IPC分类号： G11C700

CPC分类号： G11C29/025 ,  G11C11/401 ,  G11C29/006 ,  G11C29/02 ,  G11C29/50

摘要： A wafer burn-in test circuit of a semiconductor memory device having a plurality of memory cells arranged in a row/column matrix, is provided, including:a sub word line driver connected to first and second word line groups each connected to true cells and complement cells forming the memory cells, and responding to a predecoded low address; and first and second power lines respectively supplying power to the corresponding first and second power line groups by a switching operation of the sub word line driver, wherein a ground power source is applied to the first and second power lines during a normal operation, and the ground power source and a step-up power source are alternately applied to the first and second power lines during a wafer burn-in test operation.

摘要翻译： 提供了具有以行/列矩阵排列的多个存储单元的半导体存储器件的晶片老化测试电路，包括：连接到每个连接到真实单元的第一和第二字线组的子字线驱动器，以及 形成存储器单元的补码单元，以及对预解码的低地址的响应; 以及分别通过子字线驱动器的切换操作向对应的第一和第二电力线组提供电力的第一和第二电力线，其中在正常操作期间将地电源施加到第一和第二电力线，并且 接地电源和升压电源在晶片老化测试操作期间交替施加到第一和第二电源线。

公开(公告)号：US6075384A

公开(公告)日：2000-06-13

申请号：US49739

申请日：1998-03-27

申请人： Jae-Yoon Sim ,  Hong-Joon Park ,  Soo-In Cho ,  Jung-Bae Lee

发明人： Jae-Yoon Sim ,  Hong-Joon Park ,  Soo-In Cho ,  Jung-Bae Lee

IPC分类号： H03K17/00 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/018592

摘要： A bidirectional input/output buffer operates in a current mode to increase the data transfer rate between devices connected by a bidirectional transmission line. The buffer includes an output current source for generating an output current responsive to a data output signal. The output current is combined with an output current indicative of a data input signal received from another device over a transmission line, thereby forming a mixed current signal. The data input signal is restored from the mixed signal by a restoring circuit that compares the mixed signal to a reference current that depends on the value of the data output signal. The restoring circuit includes a current mirror and a reference current source that generates a reference current in response to the data output signal. To provide additional performance, an embodiment of a bidirectional input/output buffer utilizes a switchless structure having two comparators that compare the mixed signal to two different reference signals, thereby generating two comparison signals. A selector circuit selects one of the two comparison signals as the restored data input signal responsive to the data output signal.

摘要翻译： 双向输入/输出缓冲器以当前模式工作，以增加通过双向传输线连接的设备之间的数据传输速率。 缓冲器包括用于响应于数据输出信号产生输出电流的输出电流源。 输出电流与表示通过传输线从另一设备接收的数据输入信号的输出电流组合，从而形成混合电流信号。 数据输入信号通过将混合信号与取决于数据输出信号的值的参考电流进行比较的恢复电路从混合信号中恢复。 恢复电路包括响应于数据输出信号产生参考电流的电流镜和参考电流源。 为了提供额外的性能，双向输入/输出缓冲器的实施例利用具有两个比较器的无开关结构，其将混合信号与两个不同的参考信号进行比较，从而产生两个比较信号。 选择器电路根据数据输出信号选择两个比较信号中的一个作为恢复的数据输入信号。

公开(公告)号：US5659519A

公开(公告)日：1997-08-19

申请号：US585597

申请日：1996-01-16

申请人： Hyun-Seok Lee ,  Soo-In Cho

发明人： Hyun-Seok Lee ,  Soo-In Cho

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C5/145

摘要： A semiconductor memory device including at least two boosting voltage circuits which independently boost a supply voltage power level to a boosted voltage power level. A plurality of memory cell arrays each input the supply voltage power and store information therein. Driving circuits are connected to each of the memory cell arrays and supply the boosted voltage power to the memory cell arrays, the number of driving circuits preferably corresponding to the number of the boosting voltage circuits.

摘要翻译： 一种半导体存储器件，包括至少两个升压电压电路，其独立地将电源电压功率电平升高到提升的电压功率电平。 多个存储单元阵列分别输入电源电压并存储信息。 驱动电路连接到每个存储单元阵列，并将提升的电压电力提供给存储单元阵列，驱动电路的数量优选地对应于升压电压电路的数量。

公开(公告)号：US5446697A

公开(公告)日：1995-08-29

申请号：US068547

申请日：1993-05-28

申请人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

发明人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

IPC分类号： G11C5/14 ,  H02M3/07 ,  G11C13/00

CPC分类号： H02M3/07 ,  G11C5/145

摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

摘要翻译： 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

公开(公告)号：US5343438A

公开(公告)日：1994-08-30

申请号：US9475

申请日：1993-02-01

申请人： Yun-Ho Choi ,  Dae-Je Chin ,  Ejaz U. Haq ,  Soo-In Cho

发明人： Yun-Ho Choi ,  Dae-Je Chin ,  Ejaz U. Haq ,  Soo-In Cho

IPC分类号： G11C11/401 ,  G06F12/02 ,  G11C8/18 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C11/4076

摘要： The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory for accomplishing high speed data access by supplying a plurality of row address strobe signals to a chip. A plurality of row address strobe signals are supplied to a plurality of pins, and each row address strobe signal is sequentially supplied with an active signal during a data access operation. Therefore, data in a plurality of memory cell arrays is accessed during one access cycle time. Thus, since a large number of random data are provided, the data access time decreases and the performance of a system can be greatly improved.

摘要翻译： 本发明涉及一种半导体存储器件，更具体地说，涉及通过向芯片提供多个行地址选通信号来实现高速数据存取的动态随机存取存储器。 多个行地址选通信号被提供给多个引脚，并且每个行地址选通信号在数据访问操作期间被依次提供有效信号。 因此，在一个访问周期时间内访问多个存储单元阵列中的数据。 因此，由于提供大量随机数据，所以数据访问时间减少，并且可以大大提高系统的性能。