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    NANO-WIRE FIELD EFFECT TRANSISTOR, METHOD FOR MANUFACTURING THE TRANSISTOR, AND INTEGRATED CIRCUIT INCLUDING THE TRANSISTOR
    21.
    发明申请
    NANO-WIRE FIELD EFFECT TRANSISTOR, METHOD FOR MANUFACTURING THE TRANSISTOR, AND INTEGRATED CIRCUIT INCLUDING THE TRANSISTOR 有权
    纳米线场效应晶体管，制造晶体管的方法和包括晶体管的集成电路

    公开(公告)号：US20110073842A1

    公开(公告)日：2011-03-31

    申请号：US12993880

    申请日：2009-06-05

    Applicant: Yongxun Liu ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

    Inventor： Yongxun Liu ,  Takashi Matsukawa ,  Kazuhiko Endo ,  Shinichi Ouchi ,  Kunihiro Sakamoto ,  Meishoku Masahara

    IPC: H01L29/786 ,  H01L21/84 ,  B82Y99/00

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

    Abstract: Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing an SOI substrate having a (100) surface orientation, and nano-wire field effect transistor where two triangular columnar members configuring the nano-wires and being made of a silicon crystal layer are arranged one above the other on an SOI substrate having a (100) surface such a way that the ridge lines of the triangular columnar members face via an insulator; processing the silicon crystal configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; and as a nanowire, processing the silicon crystal by orientation dependent wet etching into a shape where two triangular columnar members are arranged one above the other in such a way that the ridge lines of the triangular columnar members configuring the nano-wires face through the ridge lines thereof, and an integrated circuit including the nano-wire field effect transistor.

    Abstract translation: 提供一种制造纳米线场效应晶体管的方法，包括以下步骤：制备具有（100）表面取向的SOI衬底和纳米线场效应晶体管，其中构成纳米线的两个三角柱形构件由 在具有（100）表面的SOI衬底上，使三角柱状构件的棱线经由绝缘体面对，从而将硅晶体层彼此重叠地布置; 将构成SOI衬底的硅晶体加工成具有矩形横截面的立式板状构件; 并且作为纳米线，通过取向相关的湿法蚀刻将硅晶体加工成两个三角柱形部件一个在另一个上方布置的形状，使得构成纳米线的三角柱形部件的脊线面向通过脊 线，以及包括纳米线场效应晶体管的集成电路。

    SRAM DEVICE
    22.
    发明申请
    SRAM DEVICE 有权
    SRAM设备

    公开(公告)号：US20100328990A1

    公开(公告)日：2010-12-30

    申请号：US12517696

    申请日：2007-12-06

    Applicant: Shinichi Ouchi ,  Yougxun Liu ,  Meishoku Masahara ,  Takashi Matsukawa ,  Kazuhiko Endo

    Inventor： Shinichi Ouchi ,  Yougxun Liu ,  Meishoku Masahara ,  Takashi Matsukawa ,  Kazuhiko Endo

    IPC: G11C11/412

    CPC classification number: H01L27/1203 ,  G11C11/412 ,  G11C11/413 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/785

    Abstract: An SRAM device comprising a memory cell, the memory cell comprising two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, and wherein a first bias voltage is applied to bias voltage input gates of the transistors of the memory cells in a row including a memory cell being accessed for reading or writing such that the threshold voltage on the logic signal input gates of the transistors is set at low level, and a second bias voltage is applied to the bias voltage input gates of the transistors of the memory cells in a row including a memory cell under memory holding operation such that the threshold voltage on the logic signal input gates of the transistors is set at high level.

    Abstract translation: 一种SRAM器件，包括存储单元，所述存储单元包括连接到字线的两个存取晶体管和具有互补晶体管的触发器电路，所述晶体管是具有立方半导体薄板的场效应晶体管，逻辑信号输入栅极 以及偏置电压输入栅极，所述栅极夹着半导体薄板并彼此电分离，并且其中第一偏置电压被施加到包括存储器单元的行中的存储器单元的晶体管的偏置电压输入栅极， 访问用于读取或写入，使得晶体管的逻辑信号输入栅极上的阈值电压被设置为低电平，并且第二偏置电压被施加到包括存储器的行中的存储器单元的晶体管的偏置电压输入栅极 在存储器保持操作下的存储单元，使得晶体管的逻辑信号输入栅极上的阈值电压被设置为高电平。

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