公开(公告)号：US06670667B2

公开(公告)日：2003-12-30

申请号：US10213061

申请日：2002-08-06

Applicant: Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

Inventor： Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

IPC: H01L27108

CPC classification number: H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4983

Abstract: A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.

公开(公告)号：US06458646B1

公开(公告)日：2002-10-01

申请号：US09608019

申请日：2000-06-30

Applicant: Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

Inventor： Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

IPC: H01L218242

CPC classification number: H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4983

Abstract: A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.

Abstract translation: 一种存储器件结构，包括其中形成有一个或多个非对称栅极的阵列器件区域，其中每个非对称栅极包括具有基本上垂直的侧壁的第一边缘和具有多晶硅台阶段的第二边缘，以及包括一个或多个 形成在其中的图案化栅极导体，其中支撑装置区域中的每个图案化栅极导体包括具有基本垂直侧壁的边缘。 该结构还可以包括位于阵列器件区域和支撑器件区域之间的电路器件区域，所述芯部器件区域包括一个或多个图案化栅极，每个栅极包括在栅极的每一侧上的多晶硅阶梯段。

公开(公告)号：US5421787A

公开(公告)日：1995-06-06

申请号：US947061

申请日：1992-09-18

Applicant: Wayne Ellis

Inventor： Wayne Ellis

IPC: B23Q5/16 ,  F16H9/12 ,  F16H7/08

CPC classification number: B23Q5/162 ,  F16H9/12

Abstract: The invention effects an increase in the range of continuously variable tool speed and torque control for machine tools beyond that conventionally available for operation from single phase alternating current. Interactive operator control of mechanical speed regulation is additively coupled to electrical control of direct current motor drive to reduce or eliminate machine down time needed for performing a series of varied machine operations.

Abstract translation: 本发明对于机械工具的连续可变刀具速度和转矩控制的范围的增加超出了常规可用于单相交流电的操作。 机械速度调节的交互式操作员控制与直流电动机驱动的电气控制相加耦合，以减少或消除执行一系列不同机器操作所需的停机时间。