公开(公告)号：US20130127697A1

公开(公告)日：2013-05-23

申请号：US13458026

申请日：2012-04-27

Applicant: Nan-Ying LIN ,  Yu-Hsin TING ,  Chung-Lung LI ,  Chung-Lin FU ,  Wei-Chun HSU ,  Pei-Hua CHEN

Inventor： Nan-Ying LIN ,  Yu-Hsin TING ,  Chung-Lung LI ,  Chung-Lin FU ,  Wei-Chun HSU ,  Pei-Hua CHEN

IPC: G09G3/36 ,  H03K17/56

CPC classification number: G09G3/3611 ,  G09G2310/0297

Abstract: A multiplexer circuit includes multiple groups of switches and multiple groups of control lines. Each control line in each one of the groups of control lines is coupled to a control end of at least one switch in corresponding one of the groups of switches, and each group of control lines is configured for synchronously transmitting an identical group of control signals. A display panel and method for transmitting signals in a display panel is also disclosed herein.

Abstract translation: 多路复用器电路包括多组开关和多组控制线。 每组控制线路中的每一组中的每个控制线耦合到开关组中的相应一组中的至少一个开关的控制端，并且每组控制线被配置为同步地发送相同的一组控制信号。 本文还公开了一种用于在显示面板中传输信号的显示面板和方法。

公开(公告)号：US07830352B2

公开(公告)日：2010-11-09

申请号：US11332922

申请日：2006-01-17

Applicant: Xuan-Fang Shi ,  Yu-Hsin Ting ,  Jian-Shen Yu

Inventor： Xuan-Fang Shi ,  Yu-Hsin Ting ,  Jian-Shen Yu

IPC: G09G3/36 ,  G11C19/00

CPC classification number: G09G3/3688 ,  G09G3/3648 ,  G09G2310/0248

Abstract: A driving circuit. The driving circuit includes a plurality of scan shift register cells, a pair of complementary clock signal lines, and a horizontal start signal generator. Each scan shift register cell comprises a bidirectional circuit, a shift register coupled to the bidirectional circuit, a transmission gate coupled to the shift register, and a data line coupled to the transmission gate. The complementary clock signal lines are coupled to the shift registers. The horizontal start signal generator provides a horizontal start signal to the bidirectional circuits in the first and a subsequent scan shift register cells. The shift register in each scan shift register cell provides an output signal to the bidirectional circuit in the next scan shift register cell. The bidirectional circuit in each scan shift register cell also receives the output signal from the shift register in the next scan shift register cell.

Abstract translation: 驱动电路。 驱动电路包括多个扫描移位寄存器单元，一对互补时钟信号线和水平启动信号发生器。 每个扫描移位寄存器单元包括双向电路，耦合到双向电路的移位寄存器，耦合到移位寄存器的传输门，以及耦合到传输门的数据线。 互补时钟信号线耦合到移位寄存器。 水平启动信号发生器向第一和随后的扫描移位寄存器单元中的双向电路提供水平启动信号。 每个扫描移位寄存器单元中的移位寄存器向下一个扫描移位寄存器单元中的双向电路提供输出信号。 每个扫描移位寄存器单元中的双向电路还从下一个扫描移位寄存器单元中的移位寄存器接收输出信号。

公开(公告)号：US20100112773A1

公开(公告)日：2010-05-06

申请号：US12652169

申请日：2010-01-05

Applicant: Yu-Hsin TING

Inventor： Yu-Hsin TING

IPC: H01L21/02

CPC classification number: G02F1/136213 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3265

Abstract: A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer.

Abstract translation: 提供了包括至少一个晶体管，第一存储电容器，第一导电层，层间介电层，第二导电层，钝化层和第三导电层的像素结构。 第一存储电容器电连接到晶体管。 具有至少一个第一开口的层间绝缘层覆盖第一导电层。 第二导电层形成在层间电介质层的一部分上，并通过第一开口与第一导电层电连接。 具有至少一个第二开口的钝化层覆盖晶体管和第二导电层。 第三导电层形成在钝化层的一部分上，并通过第二开口与晶体管电连接。 第一存储电容器由第三导电层，钝化层和第二导电层形成。

公开(公告)号：US20090284483A1

公开(公告)日：2009-11-19

申请号：US12255878

申请日：2008-10-22

Applicant: Yu-Hsin Ting ,  Chee-Wai Lau ,  Ming-Tien Lin ,  Chung-Lung Li ,  Heng-Sheng Chou

Inventor： Yu-Hsin Ting ,  Chee-Wai Lau ,  Ming-Tien Lin ,  Chung-Lung Li ,  Heng-Sheng Chou

IPC: G06F3/041

CPC classification number: G06F3/044 ,  G06F3/0412

Abstract: A display device and method having a sensing function is described. The device includes a liquid crystal display (LCD) panel and plural sense lines. The LCD panel includes a plurality of data lines and a plurality of gate lines. Each of the data lines is connected electrically to a plurality of left pixels and a plurality of right pixels. The sense line is disposed between each two adjacent data lines, and each of the sense lines is configured to be parallel to the data lines and perpendicular to the gate lines. The sense lines are used to transmit touch signals.

Abstract translation: 描述具有感测功能的显示装置和方法。 该装置包括液晶显示器（LCD）面板和多条感测线。 LCD面板包括多条数据线和多条栅极线。 每条数据线与多个左像素和多个右像素电连接。 感测线设置在每个两个相邻数据线之间，并且每个感测线被配置为平行于数据线并垂直于栅极线。 感测线用于传输触摸信号。

公开(公告)号：US20090278783A1

公开(公告)日：2009-11-12

申请号：US12348490

申请日：2009-01-05

Applicant: Yu-hsin Ting ,  Chung-lin Fu ,  Chun-yen Liu

Inventor： Yu-hsin Ting ,  Chung-lin Fu ,  Chun-yen Liu

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/0281

Abstract: A display device includes a substrate, a display area, an ASIC disposed by a first edge of the display area for generating a number of P data voltage signals, a first shift register having a plurality of first shift register units disposed by a second edge of the display area, a second shift register having a plurality of second shift register units disposed by a third edge of the display area, a plurality of first switch unit and a plurality of second units. The first switch units sequentially outputs the first through the P 2  th data voltage signals to the display area in response to first control signal from the first shift register units, simultaneously, the second switch units sequentially outputs the ( P 2 + 1 )  th through the Pth data voltage signals to the display area in response to second control signal from the second shift register units.

Abstract translation: 显示装置包括基板，显示区域，由显示区域的第一边缘设置的ASIC，用于产生多个P数据电压信号;第一移位寄存器，具有多个第一移位寄存器单元， 显示区域，具有由显示区域的第三边缘布置的多个第二移位寄存器单元的第二移位寄存器，多个第一开关单元和多个第二单元。 第一开关单元响应于来自第一移位寄存器单元的第一控制信号，顺序地将第一至第二数据电压信号输出到显示区域，同时第二开关单元依次输出（P 2 + 1） 响应于来自第二移位寄存器单元的第二控制信号，通过Pth数据电压信号传送到显示区域。

公开(公告)号：US09007541B2

公开(公告)日：2015-04-14

申请号：US13615598

申请日：2012-09-14

Applicant: Szu-Chieh Chen ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  I-Fang Chen ,  Yi-Xuan Hung ,  Da-Wei Fan

Inventor： Szu-Chieh Chen ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  I-Fang Chen ,  Yi-Xuan Hung ,  Da-Wei Fan

IPC: G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/136286 ,  H01L27/1255

Abstract: A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same.

Abstract translation: 提供像素阵列和显示面板。 像素阵列包括多个像素单元。 每个像素单元包括第一扫描线，第二扫描线，数据线，第一薄膜晶体管，第二薄膜晶体管，第一像素电极和第二像素电极。 第一薄膜晶体管电连接到第一扫描线和数据线。 第一像素电极电连接到第一薄膜晶体管。 第二薄膜晶体管电连接到第二扫描线和数据线。 第二像素电极电连接到第二薄膜晶体管。 XY平面上的第一薄膜晶体管的正交投影图案和XY平面上的第二薄膜晶体管的正交投影图案基本相同。

公开(公告)号：US08982031B2

公开(公告)日：2015-03-17

申请号：US13610900

申请日：2012-09-12

Applicant: Yi-Xuan Hung ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  Szu-Chieh Chen ,  Da-Wei Fan ,  Chung-Lin Fu

Inventor： Yi-Xuan Hung ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  Szu-Chieh Chen ,  Da-Wei Fan ,  Chung-Lin Fu

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0218 ,  G09G2310/0275 ,  G09G2310/0281 ,  G09G2310/0297

Abstract: A display panel includes a plurality of first driving switches installed at a first side of the display panel, a plurality of second switches installed at a second side of the display panel, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, and a plurality of pixels. Each of the first driving switches includes a first input end and a plurality of first output ends. Each of the second driving switches includes a second input end and a plurality of second output ends. The first data lines are electrically connected to the first output ends. The second data lines are electrically connected to the second output ends. The plurality of pixels are electrically connected to the plurality of first data lines, second data lines and scan lines for displaying images. The first data lines and the second data lines are arranged interlacedly.

Abstract translation: 显示面板包括安装在显示面板的第一侧的多个第一驱动开关，安装在显示面板的第二侧的多个第二开关，多个第一数据线，多条第二数据线， 多个扫描线，以及多个像素。 每个第一驱动开关包括第一输入端和多个第一输出端。 每个第二驱动开关包括第二输入端和多个第二输出端。 第一数据线电连接到第一输出端。 第二数据线电连接到第二输出端。 多个像素电连接到多个第一数据线，第二数据线和用于显示图像的扫描线。 第一数据线和第二数据线被交错布置。

公开(公告)号：US20140035896A1

公开(公告)日：2014-02-06

申请号：US13567582

申请日：2012-08-06

Applicant: Nan-Ying Lin ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Pei-Hua Chen

Inventor： Nan-Ying Lin ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Pei-Hua Chen

IPC: G06F3/038

CPC classification number: G09G3/3611 ,  G09G3/3685 ,  G09G2310/0297

Abstract: In one aspect, an LCD includes a display panel with a pixel matrix having M scan lines and N data lines, and a multiplexer feed-through compensation circuit, which includes P signal lines for providing P video signals, P multiplexers, and K pairs of control lines providing K pairs of control signals. Each multiplexer is electrically coupled to a corresponding signal line and has K channels. Each channel includes first and second switches parallel-connected between the signal line and a corresponding data line for selectively transmitting the video signal to the corresponding data line. Each pair of control lines is respectively electrically coupled to the first and second switches of a corresponding channel of each multiplexer. Each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other switch.

Abstract translation: 一方面，LCD包括具有M条扫描线和N条数据线的像素矩阵的显示面板和多路复用器馈通补偿电路，其包括用于提供P视频信号的P信号线，P多路复用器和K对 提供K对控制信号的控制线。 每个复用器电耦合到对应的信号线并且具有K个信道。 每个通道包括并联在信号线和相应的数据线之间的第一和第二开关，用于选择性地将视频信号传输到对应的数据线。 每对控制线分别电耦合到每个多路复用器的相应通道的第一和第二开关。 每对控制信号被配置为使得关闭第一和第二开关中的一个的时间早于关闭另一个开关的时间。

公开(公告)号：US20130135284A1

公开(公告)日：2013-05-30

申请号：US13458465

申请日：2012-04-27

Applicant: Chien-Chang TSENG ,  Kuang-Hsiang Liu ,  Yu-Hsin Ting ,  Shih-Hsiang Chou ,  Ting-Jui Chang

Inventor： Chien-Chang TSENG ,  Kuang-Hsiang Liu ,  Yu-Hsin Ting ,  Shih-Hsiang Chou ,  Ting-Jui Chang

IPC: G09G5/00

CPC classification number: G11C19/28 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2330/021

Abstract: A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.

Abstract translation: 门驱动器包括级联连接的驱动级。 每个驱动级包括第一移位寄存器电路和第二移位寄存器电路。 第一移位寄存器电路被配置为输出当前级驱动信号和下一级驱动信号。 第二移位寄存器电路电耦合到第一移位寄存器电路，并被配置为输出当前级门信号，第一下级门信号和第二下级门信号。 此外，还提供了显示面板。

公开(公告)号：US20130127801A1

公开(公告)日：2013-05-23

申请号：US13610900

申请日：2012-09-12

Applicant: Yi-Xuan Hung ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  Szu-Chieh Chen ,  Da-Wei Fan ,  Chung-Lin Fu

Inventor： Yi-Xuan Hung ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  Szu-Chieh Chen ,  Da-Wei Fan ,  Chung-Lin Fu

IPC: G06F3/038

CPC classification number: G09G3/20 ,  G09G2310/0218 ,  G09G2310/0275 ,  G09G2310/0281 ,  G09G2310/0297

Abstract: A display panel includes a plurality of first driving switches installed at a first side of the display panel, a plurality of second switches installed at a second side of the display panel, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, and a plurality of pixels. Each of the first driving switches includes a first input end and a plurality of first output ends. Each of the second driving switches includes a second input end and a plurality of second output ends. The first data lines are electrically connected to the first output ends. The second data lines are electrically connected to the second output ends. The plurality of pixels are electrically connected to the plurality of first data lines, second data lines and scan lines for displaying images. The first data lines and the second data lines are arranged interlacedly.

Abstract translation: 显示面板包括安装在显示面板的第一侧的多个第一驱动开关，安装在显示面板的第二侧的多个第二开关，多个第一数据线，多个第二数据线， 多个扫描线，以及多个像素。 每个第一驱动开关包括第一输入端和多个第一输出端。 每个第二驱动开关包括第二输入端和多个第二输出端。 第一数据线电连接到第一输出端。 第二数据线电连接到第二输出端。 多个像素电连接到多个第一数据线，第二数据线和用于显示图像的扫描线。 第一数据线和第二数据线被交错布置。