公开(公告)号：US20130155035A1

公开(公告)日：2013-06-20

申请号：US13609310

申请日：2012-09-11

Applicant: Szu-Chieh CHEN ,  Yu-Hsin TING ,  Chung-Lung LI ,  Chen-Ming CHEN ,  I-Fang CHEN ,  Yun-Chung LIN ,  Da-Yei FAN ,  Yi-Xuan HUNG ,  Chun-Yu HUANG

Inventor： Szu-Chieh CHEN ,  Yu-Hsin TING ,  Chung-Lung LI ,  Chen-Ming CHEN ,  I-Fang CHEN ,  Yun-Chung LIN ,  Da-Yei FAN ,  Yi-Xuan HUNG ,  Chun-Yu HUANG

IPC: G06F3/038

CPC classification number: G09G3/20 ,  G09G3/2003 ,  G09G2310/0251 ,  G09G2310/0254 ,  G09G2310/067 ,  G09G2320/0209

Abstract: A method for driving a pixel circuit, which is adapted to drive a first pixel circuit coupled to a first gate line and a second pixel circuit coupled to a second gate line, is disclosed. The first pixel circuit receives display data before the second pixel circuit does. The method provides only one first enable pulse to the first gate line in a frame, and provides a second enable pulse and a third enable pulse to the second gate line in the same frame. The starting time of the second enable pulse is in an enabled time period of the first enable pulse, and the enabled time period of the third enable pulse is after the enabled time periods of the first and second enable pulses.

Abstract translation: 公开了一种用于驱动适于驱动耦合到第一栅极线的第一像素电路和耦合到第二栅极线的第二像素电路的像素电路的方法。 第一像素电路接收第二像素电路之前的显示数据。 该方法仅向帧中的第一栅极线提供一个第一使能脉冲，并且在同一帧中向第二栅极线提供第二使能脉冲和第三使能脉冲。 第二使能脉冲的开始时间处于第一使能脉冲的使能时间段中，并且第三使能脉冲的使能时间段在第一和第二使能脉冲的使能时间段之后。

公开(公告)号：US20130127697A1

公开(公告)日：2013-05-23

申请号：US13458026

申请日：2012-04-27

Applicant: Nan-Ying LIN ,  Yu-Hsin TING ,  Chung-Lung LI ,  Chung-Lin FU ,  Wei-Chun HSU ,  Pei-Hua CHEN

Inventor： Nan-Ying LIN ,  Yu-Hsin TING ,  Chung-Lung LI ,  Chung-Lin FU ,  Wei-Chun HSU ,  Pei-Hua CHEN

IPC: G09G3/36 ,  H03K17/56

CPC classification number: G09G3/3611 ,  G09G2310/0297

Abstract: A multiplexer circuit includes multiple groups of switches and multiple groups of control lines. Each control line in each one of the groups of control lines is coupled to a control end of at least one switch in corresponding one of the groups of switches, and each group of control lines is configured for synchronously transmitting an identical group of control signals. A display panel and method for transmitting signals in a display panel is also disclosed herein.

Abstract translation: 多路复用器电路包括多组开关和多组控制线。 每组控制线路中的每一组中的每个控制线耦合到开关组中的相应一组中的至少一个开关的控制端，并且每组控制线被配置为同步地发送相同的一组控制信号。 本文还公开了一种用于在显示面板中传输信号的显示面板和方法。

公开(公告)号：US20100112773A1

公开(公告)日：2010-05-06

申请号：US12652169

申请日：2010-01-05

Applicant: Yu-Hsin TING

Inventor： Yu-Hsin TING

IPC: H01L21/02

CPC classification number: G02F1/136213 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3265

Abstract: A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer.

Abstract translation: 提供了包括至少一个晶体管，第一存储电容器，第一导电层，层间介电层，第二导电层，钝化层和第三导电层的像素结构。 第一存储电容器电连接到晶体管。 具有至少一个第一开口的层间绝缘层覆盖第一导电层。 第二导电层形成在层间电介质层的一部分上，并通过第一开口与第一导电层电连接。 具有至少一个第二开口的钝化层覆盖晶体管和第二导电层。 第三导电层形成在钝化层的一部分上，并通过第二开口与晶体管电连接。 第一存储电容器由第三导电层，钝化层和第二导电层形成。