公开(公告)号：US11289133B2

公开(公告)日：2022-03-29

申请号：US14855687

申请日：2015-09-16

Applicant: ARM Limited

Inventor： Alex James Waugh

IPC: G06F1/3234 ,  G06F12/0811 ,  G11C5/14

Abstract: There is provided an apparatus comprising power state determination circuitry to determine a power state of a processing circuit; and control circuitry to issue a control signal relating to an item of data stored in a first storage circuitry. When the power state of the processing circuit is a predetermined state, the control circuitry issues a further control signal to a second storage circuitry to indicate whether the item of data is to be retained by the second storage circuitry.

公开(公告)号：US10931799B2

公开(公告)日：2021-02-23

申请号：US16417925

申请日：2019-05-21

Applicant: Arm Limited

Inventor： João Carlos Mateus da Silva Martins ,  Alex James Waugh

IPC: H04L29/14 ,  H04L12/823 ,  H04L12/715 ,  H04L29/06 ,  H04L12/841

Abstract: An apparatus for handling resets corresponding to multiple reset domains comprises a transport network interconnecting elements to enable data to be transferred from one element to another, ingress circuitry to couple elements to the transport network, and egress circuitry to couple the transport network to the elements. The ingress circuitry couples source elements to the transport network, and is responsive to receiving data from a source element to generate at least one transport packet in order to send that data over the transport network. Each transport packet comprises a reset domain indicator indicative of the reset domain in which the source element operates. The egress circuitry couples the transport network to destination elements and, whilst a reset of a particular reset domain is asserted, discards transport packets for which the reset domain indicator indicates the particular reset domain.

公开(公告)号：US10891084B2

公开(公告)日：2021-01-12

申请号：US16353257

申请日：2019-03-14

Applicant: Arm Limited

Inventor： Alex James Waugh ,  Geoffray Mattheiu Lacourba ,  Andrew John Turner ,  Sergio Schuler

IPC: G06F3/06 ,  G06F9/50 ,  G06F13/16 ,  G06F12/0837 ,  G06F9/54

Abstract: Aspects of the present disclosure relate to an interconnect comprising an interface to couple to a master device, the interface comprising buffer storage. The interface is configured to receive a request from the master device for data comprising a plurality of data blocks, the master device requiring the data blocks in a defined order. A data collator is configured to: receive the request; issue a data pull request to cause the interface to allocate buffer space in the buffer storage for buffering the requested data; and responsive to receiving a confirmation that the buffer space is allocated, provide the requested data to the buffer storage. The interface is configured to employ the buffer storage to enable re-ordering of the plurality of data blocks of the requested data, prior to outputting the plurality of data blocks to the master device; and output the plurality of data blocks to the master device in the defined order.

公开(公告)号：US10198360B2

公开(公告)日：2019-02-05

申请号：US14867454

申请日：2015-09-28

Applicant: ARM LIMITED

Inventor： Alex James Waugh

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1027 ,  G06F11/07

Abstract: There is provided a data processing apparatus comprising: processing circuitry to speculatively execute an instruction referencing a virtual address. Lookup circuitry receives the virtual address from the processing circuitry. The lookup circuitry comprises storage circuitry to store at least one virtual address and page walking circuitry to perform a page walk on further storage circuitry, in dependence on the virtual address being unlisted by the storage circuitry, to determine whether a correspondence between a physical address and the virtual address exists. The lookup circuitry signals an error when the correspondence cannot be found and, in response to the error being signaled, the storage circuitry stores an entry comprising the virtual address.