公开(公告)号：US11915005B1

公开(公告)日：2024-02-27

申请号：US17960390

申请日：2022-10-05

Applicant: Arm Limited

Inventor： Chang Joo Lee ,  Michael Brian Schinzler ,  Yasuo Ishii ,  Sergio Schuler

IPC: G06F9/38

CPC classification number: G06F9/3844

Abstract: A data processing apparatus includes receive circuitry that receives an indication of a trigger block of instructions. Branch prediction circuitry provides, in response to the trigger block of instructions, branch predictions in respect of a branch within: a subsequent block of instructions subsequent to the trigger block of instructions in execution order, when in a 1-taken mode of operation and a later block of instructions subsequent to the subsequent block of instructions in execution order, when in a 2-taken mode of operation

公开(公告)号：US10891084B2

公开(公告)日：2021-01-12

申请号：US16353257

申请日：2019-03-14

Applicant: Arm Limited

Inventor： Alex James Waugh ,  Geoffray Mattheiu Lacourba ,  Andrew John Turner ,  Sergio Schuler

IPC: G06F3/06 ,  G06F9/50 ,  G06F13/16 ,  G06F12/0837 ,  G06F9/54

Abstract: Aspects of the present disclosure relate to an interconnect comprising an interface to couple to a master device, the interface comprising buffer storage. The interface is configured to receive a request from the master device for data comprising a plurality of data blocks, the master device requiring the data blocks in a defined order. A data collator is configured to: receive the request; issue a data pull request to cause the interface to allocate buffer space in the buffer storage for buffering the requested data; and responsive to receiving a confirmation that the buffer space is allocated, provide the requested data to the buffer storage. The interface is configured to employ the buffer storage to enable re-ordering of the plurality of data blocks of the requested data, prior to outputting the plurality of data blocks to the master device; and output the plurality of data blocks to the master device in the defined order.