公开(公告)号：US20180101489A1

公开(公告)日：2018-04-12

申请号：US15567696

申请日：2016-03-09

Applicant: ARM LIMITED

Inventor： Dominic William BROWN ,  Christopher Vincent SEVERINO ,  Ashley John CRAWFORD ,  Andrew Brookfield SWAINE

IPC: G06F13/362 ,  G06F1/32 ,  G06F13/38

CPC classification number: G06F13/362 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/325 ,  G06F1/3296 ,  G06F13/385 ,  Y02D10/151

Abstract: A data processing apparatus (2) has a number of devices (4) having a normal state and a quiescent state. Transition sequencing circuitry (70) controls a sequential state transition process for transitioning each of the devices (4) in turn between the normal state and the quiescent state. For each device, the transition sequencing circuitry (70) controls the transition based on at least one preference indication transmitted from that device (4) providing an indication of a preference to operating the normal state or the quiescent state.

公开(公告)号：US20160011985A1

公开(公告)日：2016-01-14

申请号：US14736770

申请日：2015-06-11

Applicant: ARM LIMITED

Inventor： Andrew Brookfield SWAINE ,  Gareth EVANS ,  Matthew Lucien EVANS

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/1027 ,  G06F13/405 ,  G06F2212/1016 ,  G06F2212/65

Abstract: A data processing apparatus 2 includes bridge circuitry 14, 16, 18 which serves to translate memory transactions of a first type (AXI) into memory transactions of a second type (PCI Express). The bridge circuitry includes translation circuitry 18 which maps at least some of the bits of attribute data of a memory transaction of the first type to unused bits within the significant bits of an address of the second type, which are unused to represent significant bits of the address of memory transactions of the first type.

Abstract translation: 数据处理装置2包括用于将第一类型（AXI）的存储器事务转换为第二类型（PCI Express）的存储器事务的桥接电路14,16,18。 桥接电路包括转换电路18，其将第一类型的存储器事务的属性数据的位的至少一些位映射到第二类型的地址的有效位内的未使用位，其未被用于表示第二类型的有效位 第一类内存交易的地址。