公开(公告)号：US11614985B2

公开(公告)日：2023-03-28

申请号：US17130474

申请日：2020-12-22

Applicant: Arm Limited

Inventor： Alexander Donald Charles Chadwick ,  Andrew Brookfield Swaine ,  Gareth James Evans ,  Jonathan Curtis Beard

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/06

Abstract: An apparatus comprises memory access circuitry to access a memory system; a plurality of memory mapped registers, including at least an insert register and a producer pointer register; and control circuitry to perform an insert operation in response to receipt of an insert request from a requester device sharing access to the memory system. The insert request specifies an address mapped to the insert register and an indication of a payload. The insert operation includes controlling the memory access circuitry to write the payload to a location in the memory system selected based on a producer pointer value stored in the producer pointer register, and updating the producer pointer register to increment the producer pointer value.

公开(公告)号：US11379152B2

公开(公告)日：2022-07-05

申请号：US16898781

申请日：2020-06-11

Applicant: Arm Limited

Inventor： Andrew Brookfield Swaine ,  Peter Andrew Riocreux

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/1027

Abstract: An apparatus comprises transaction handling circuitry to issue memory access transactions, each memory access transaction specifying an epoch identifier indicative of a current epoch in which the memory access transaction is issued; transaction tracking circuitry to track, for each of at least two epochs, a number of outstanding memory access transactions issued in that epoch; barrier termination circuitry to signal completion of a barrier termination command when the transaction tracking circuitry indicates that there are no outstanding memory access transactions remaining which were issued in one or more epochs preceding a barrier point; and epoch changing circuitry to change the current epoch to a next epoch, in response to a barrier point signal representing said barrier point. This helps to reduce the circuit area overhead for tracking completion of memory access transactions preceding a barrier point.

公开(公告)号：US20220027283A1

公开(公告)日：2022-01-27

申请号：US16937272

申请日：2020-07-23

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt ,  Andrew Brookfield Swaine

IPC: G06F12/0895 ,  G06T1/20

Abstract: A data processing system is provided comprising a cache system configured to transfer data between a processor and memory system. The cache system comprises a cache. When a block of data that is stored in the memory in a compressed form is to be loaded into the cache, the block of data is stored into a group of one or more cache lines of the cache and the associated compression metadata for the compressed block of data is provided as separate side band data.

公开(公告)号：US12271320B2

公开(公告)日：2025-04-08

申请号：US17906625

申请日：2021-01-26

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Andrew Brookfield Swaine ,  Yuval Elad ,  Martin Weidmann

IPC: G06F12/14 ,  G06F12/0808 ,  G06F12/1045

Abstract: Address translation circuitry (16) translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry (20) performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.

公开(公告)号：US12056058B2

公开(公告)日：2024-08-06

申请号：US17850072

申请日：2022-06-27

Applicant: Arm Limited

Inventor： Andrew David Tune ,  Andrew Brookfield Swaine

IPC: G06F12/121 ,  G06F12/06 ,  G06F12/0891

CPC classification number: G06F12/121 ,  G06F12/0646 ,  G06F12/0891

Abstract: An apparatus comprises a cache comprising a plurality of cache entries, and cache replacement control circuitry to select, in response to a cache request specifying a target address missing in the cache, a victim cache entry to be replaced with a new cache entry. The cache request specifies a partition identifier indicative of an execution environment associated with the cache request. The victim cache entry is selected based on re-reference interval prediction (RRIP) values for a candidate set of cache entries. The RRIP value for a given cache entry is indicative of a relative priority with which the given cache entry is to be selected as the victim cache entry. Configurable replacement policy configuration data is selected based on the partition identifier, and the RRIP value of the new cache entry is set to an initial value selected based on the selected configurable replacement policy configuration data.

公开(公告)号：US11853226B2

公开(公告)日：2023-12-26

申请号：US16624430

申请日：2018-05-15

Applicant: ARM LIMITED

Inventor： Andrew Brookfield Swaine

IPC: G06F12/00 ,  G06F12/1036 ,  G06F12/0864 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F12/0864 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/651 ,  G06F2212/657

Abstract: An apparatus has an address translation cache (12, 16) having a number of cache entries (40) for storing address translation data which depends on one or more page table entries of page tables. Control circuitry (50) is responsive to an invalidation request specifying address information to perform an invalidation lookup operation to identify at least one target cache entry to be invalidated. The target cache entry is an entry for which the corresponding address translation data depends on at least one target page table entry corresponding to the address information. The control circuitry (50) selects one of a number of invalidation lookup modes to use for the invalidation lookup operation in dependence on page size information indicating the page size of the target page table entry. The different invalidation lookup modes correspond to different ways of identifying the target cache entry based on the address information.

公开(公告)号：US11615022B2

公开(公告)日：2023-03-28

申请号：US16943121

申请日：2020-07-30

Applicant: Arm Limited

Inventor： Lorenzo Di Gregorio ,  Andrew Brookfield Swaine

IPC: G06F12/0811 ,  G06F1/3206 ,  G06F1/3296 ,  G06F12/0815

Abstract: An apparatus is described that has processing circuitry for performing operations, and a communication path employed by the processing circuitry to access a first memory. Switch circuitry, when activated, is connected to the communication path. The processing circuitry issues access commands specifying addresses to be accessed, where each address is mapped to location in a memory system in accordance with a system address map. The memory system comprises at least the first memory and a second memory. When in a particular mode, the processing circuitry performs operations that require access to only a subset of the locations provided in the first memory. The switch circuitry is arranged, whilst the processing circuitry is in the particular mode, to be activated in order to intercept the access commands issued over the communication path that specify addresses mapped by the system address map to locations within the subset of locations. Those intercepted access commands are redirected to locations within the second memory that are otherwise unused whilst the processing circuitry is in the particular mode. This can provide significant power consumption benefits.

公开(公告)号：US11507515B1

公开(公告)日：2022-11-22

申请号：US17361822

申请日：2021-06-29

Applicant: Arm Limited

Inventor： Andrew Brookfield Swaine

IPC: G06F12/0891 ,  G06F12/0871 ,  G06F12/02 ,  G06F12/1045

Abstract: The present disclosure advantageously provides a memory management unit and methods for invalidating cache lines in address translation caches. The memory management unit has one or more address translation caches, and each address translation cache has a plurality of cache lines. The memory management unit receives transactions from a source of transactions. The transactions include, inter alia, memory transactions and a set-aside translation transaction. The memory transactions include at least a first memory transaction and a last memory transaction, and each memory transaction includes the same virtual memory address and the same translation context identifier. The set-aside translation transaction also includes the same virtual memory address and the same translation context identifier. In response to receiving the set-aside translation transaction, the memory management unit deallocates each cache line that stores an address translation for the same virtual memory address and the same translation context identifier.

公开(公告)号：US20220058121A1

公开(公告)日：2022-02-24

申请号：US17445146

申请日：2021-08-16

Applicant: Arm Limited

Inventor： Alexander Alfred Hornung ,  Andrew Brookfield Swaine

IPC: G06F12/0802 ,  G06F3/06

Abstract: Requester circuitry 4 issues an access request specifying a target physical address (PA) and a target physical address space (PAS) identifier identifying a target PAS. Prior to a point of physical aliasing (PoPA), a pre-PoPA memory system component 24, 8 treats aliasing PAs from different PASs which actually correspond to the same memory system resource as if they correspond to different memory system resources. A post-PoPA memory system component 6 treats the aliasing PAs as referring to the same memory system resource. When the target PA and target PAS of a read-if-hit-pre-PoPA request hit in a pre-PoPA cache 24, a data response is returned to the requester circuitry 4. If the read-if-hit-pre-PoPA request misses in the pre-PoPA cache 24, a no-data response is returned. The read-if-hit-pre-PoPA request is safe to issue speculatively while waiting for security checks to be performed, improving performance.

公开(公告)号：US11204879B2

公开(公告)日：2021-12-21

申请号：US16433311

申请日：2019-06-06

Applicant: Arm Limited

Inventor： Andrew Brookfield Swaine

IPC: G06F12/00 ,  G06F12/1009 ,  G06F13/42

Abstract: Circuitry comprises a transaction interface to receive a data handling transaction from an upstream device, the data handling transaction defining a target virtual memory address in a virtual memory address space; translation circuitry to access a set of address mappings between virtual memory addresses and physical memory addresses in a physical memory address space; the translation circuitry being configured to initiate handling of the data handling transaction by a downstream device according to a target physical memory address mapped from the target virtual memory address when the set of address mappings includes an address mapping for the target virtual memory address, and to provide a transaction response to the transaction interface indicating a fault condition when the set of address mappings fails to provide an address mapping for the target virtual memory address; and control circuitry to receive a memory region request from the upstream device, requesting that a memory region in the virtual memory address space including the target virtual memory address be made available, to initiate handling of the memory region request and to provide a response to the upstream device in dependence upon the handling of the memory region request.