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    Circuitry and Method
    2.
    发明公开
    Circuitry and Method 审中-公开

    公开(公告)号：US20240054073A1

    公开(公告)日：2024-02-15

    申请号：US17885780

    申请日：2022-08-11

    Applicant: Arm Limited

    Inventor： Andrew David Tune ,  Sean James Salisbury ,  Edward Martin McCombs, JR.

    IPC: G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F2212/60

    Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

    Interconnection network for integrated circuit
    3.
    发明授权
    Interconnection network for integrated circuit 有权

    公开(公告)号：US10771194B2

    公开(公告)日：2020-09-08

    申请号：US15989226

    申请日：2018-05-25

    Applicant: Arm Limited

    Inventor： Andrew David Tune ,  Guanghui Geng ,  Zheng Xu

    IPC: H04L1/00 ,  H04L12/707 ,  G06F13/40 ,  G06F17/50 ,  G06F30/30

    Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

    INTERCONNECTION NETWORK FOR INTEGRATED CIRCUIT
    4.
    发明申请
    INTERCONNECTION NETWORK FOR INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20190361770A1

    公开(公告)日：2019-11-28

    申请号：US15989224

    申请日：2018-05-25

    Applicant: Arm Limited

    Inventor： Guanghui Geng ,  Andrew David Tune

    IPC: G06F11/10 ,  G06F13/40

    Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

    RECEIVER BASED COMMUNICATION PERMISSION TOKEN ALLOCATION
    5.
    发明申请
    RECEIVER BASED COMMUNICATION PERMISSION TOKEN ALLOCATION 有权
    基于接收者的通信许可授权分配

    公开(公告)号：US20140372646A1

    公开(公告)日：2014-12-18

    申请号：US13918025

    申请日：2013-06-14

    Applicant: ARM Limited

    Inventor： Sean James SALISBURY ,  Andrew David Tune ,  Alistair Crone Bruce

    IPC: G06F13/362

    CPC classification number: G06F13/362 ,  G06F13/37

    Abstract: A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices.

    Abstract translation: 数据处理装置具有通过通信电路进行通信的主设备和从设备。 从设备与预定数量的权限令牌相关联，该权限令牌等于可由该从设备从通信电路接受用于处理的当前待定消息的最大数量。 从设备将这些权限令牌发送到主设备。 主设备占用其接收到的权限令牌的专属临时占用，使得许可令牌不再可用于任何其他主设备。 当主设备对该从设备具有独占临时拥有权限令牌时，主设备向从设备发起消息。 当主设备已经发起其消息时，它放弃对该权限令牌的独占临时拥有，使得其可用于其他设备。

    Cache replacement control
    7.
    发明授权
    Cache replacement control 有权

    公开(公告)号：US12056058B2

    公开(公告)日：2024-08-06

    申请号：US17850072

    申请日：2022-06-27

    Applicant: Arm Limited

    Inventor： Andrew David Tune ,  Andrew Brookfield Swaine

    IPC: G06F12/121 ,  G06F12/06 ,  G06F12/0891

    CPC classification number: G06F12/121 ,  G06F12/0646 ,  G06F12/0891

    Abstract: An apparatus comprises a cache comprising a plurality of cache entries, and cache replacement control circuitry to select, in response to a cache request specifying a target address missing in the cache, a victim cache entry to be replaced with a new cache entry. The cache request specifies a partition identifier indicative of an execution environment associated with the cache request. The victim cache entry is selected based on re-reference interval prediction (RRIP) values for a candidate set of cache entries. The RRIP value for a given cache entry is indicative of a relative priority with which the given cache entry is to be selected as the victim cache entry. Configurable replacement policy configuration data is selected based on the partition identifier, and the RRIP value of the new cache entry is set to an initial value selected based on the selected configurable replacement policy configuration data.

    Arbitrating circuitry and method
    8.
    发明授权
    Arbitrating circuitry and method 有权

    公开(公告)号：US10592439B2

    公开(公告)日：2020-03-17

    申请号：US16386321

    申请日：2019-04-17

    Applicant: ARM Limited

    Inventor： Andrew David Tune ,  Peter Andrew Riocreux ,  Alessandro Grande

    IPC: G06F13/14

    Abstract: Arbitrating circuitry arbitrates between a plurality of inputs and a selection of at least one of said plurality of inputs. The arbitrating circuitry includes an array of interconnected arbiter devices operating with respect to a set of Q inputs. The array comprises M sub-levels with at least a first sub-level having T arbiter devices each operating with respect to U inputs, where Q=UM and Q=TU. For each sub-level other than a first sub-level, each arbiter device in a sub-level receives as input requests signals indicating an arbitration outcome for two or more arbiter devices in a preceding sub-level and arbitrates between those input requests.

    Cache coherency
    9.
    发明授权
    Cache coherency 有权

    公开(公告)号：US10169236B2

    公开(公告)日：2019-01-01

    申请号：US15133341

    申请日：2016-04-20

    Applicant: ARM LIMITED

    Inventor： Sean James Salisbury ,  Andrew David Tune

    IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0813

    Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure, which of the cache memories are caching those memory addresses; and control circuitry configured to detect a directory entry relating to a memory address to be accessed so as to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories or a coherent agent in instances when the directory entry indicates that another of the cache memories is caching that memory address; the control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control.

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