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37 条记录 (耗时 0.019 秒)

    Data access request specifying enable vector
    2.
    发明授权
    Data access request specifying enable vector 有权

    公开(公告)号：US10929060B2

    公开(公告)日：2021-02-23

    申请号：US16037091

    申请日：2018-07-17

    申请人： Arm Limited

    发明人： Andrew David Tune

    IPC分类号： G06F3/06 ,  G06F12/06

    摘要： An integrated circuit comprises: a requesting node to issue a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion, and a control node responsive to the data access request to control at least one destination node to service at least one data access transaction. Each data access transaction is associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.

    Arbitration circuitry
    3.
    发明授权
    Arbitration circuitry 有权

    公开(公告)号：US10740269B2

    公开(公告)日：2020-08-11

    申请号：US16037117

    申请日：2018-07-17

    申请人： Arm Limited

    发明人： Andrew David Tune

    IPC分类号： G06F12/00 ,  G06F13/366 ,  G06F9/50

    摘要： Arbitration circuitry is provided for allocating up to M resources to N requesters, where M≥2. The arbitration circuitry comprises group allocation circuitry to control a group allocation in which the N requesters are allocated to M groups of requesters, with each requester allocated to one of the groups; and M arbiters each corresponding to a respective one of the M groups. Each arbiter selects a winning requester from the corresponding group, which is to be allocated a corresponding resource of the M resources. In response to a given requester being selected as the winning requester by the arbiter for a given group, the group allocation is changed so that in a subsequent arbitration cycle the given requester is in a different group to the given group.

    Interconnect and method of managing a snoop filter for an interconnect
    5.
    发明授权
    Interconnect and method of managing a snoop filter for an interconnect 有权

    公开(公告)号：US09727466B2

    公开(公告)日：2017-08-08

    申请号：US14822953

    申请日：2015-08-11

    申请人： ARM LIMITED

    发明人： Andrew David Tune ,  Sean James Salisbury

    IPC分类号： G06F12/08 ,  G06F12/0831 ,  G06F12/0808

    CPC分类号： G06F12/0833 ,  G06F12/0808 ,  G06F12/0831 ,  G06F2212/62 ,  G06F2212/621 ,  Y02D10/13

    摘要： An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage. The coherency control circuitry then responds to the snoop control data by issuing a snoop transaction to each master device indicated by the snoop control data, in order to cause a snoop operation to be performed in their associated cache storage in order to generate snoop response data. Analysis circuitry then determines from the snoop response data an update condition, and upon detection of the update condition triggers performance of an update operation within the snoop filter circuitry to update the address-dependent caching indication data. By subjecting the snoop response data to such an analysis, it is possible to identify situations where the caching indication data has become out of date, and update that caching indication data accordingly, this giving rise to significant performance benefits in the operation of the interconnect.

    Handling write requests for a data array
    6.
    发明授权
    Handling write requests for a data array 有权
    处理数据数组的写请求

    公开(公告)号：US09361236B2

    公开(公告)日：2016-06-07

    申请号：US13920685

    申请日：2013-06-18

    申请人： ARM Limited

    发明人： Andrew David Tune ,  Sean James Salisbury

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0864 ,  G06F12/0846

    摘要： A data array has multiple ways, each way having entries for storing data values. In response to a write request, an updated data value having a target address may be stored in any of a corresponding set of entries comprising an entry selected from each way based on the target address. An update queue stores update information representing pending write requests. Update information is selected from the update queue for a group of pending write requests corresponding to different ways, and these write requests are performed in parallel so that updated values are written to entries of different ways.

    摘要翻译： 数据阵列有多种方式，每种方式都有用于存储数据值的条目。 响应于写请求，具有目标地址的更新的数据值可以存储在包括从每个方式基于目标地址选择的条目的对应的一组条目中的任何一个中。 更新队列存储表示待决写入请求的更新信息。 对于与不同方式相对应的一组待决写入请求，从更新队列中选择更新信息，并且并行执行这些写请求，使得更新的值被写入不同方式的条目。

    Cache replacement control
    8.
    发明授权
    Cache replacement control 有权

    公开(公告)号：US12056058B2

    公开(公告)日：2024-08-06

    申请号：US17850072

    申请日：2022-06-27

    申请人： Arm Limited

    发明人： Andrew David Tune ,  Andrew Brookfield Swaine

    IPC分类号： G06F12/121 ,  G06F12/06 ,  G06F12/0891

    CPC分类号： G06F12/121 ,  G06F12/0646 ,  G06F12/0891

    摘要： An apparatus comprises a cache comprising a plurality of cache entries, and cache replacement control circuitry to select, in response to a cache request specifying a target address missing in the cache, a victim cache entry to be replaced with a new cache entry. The cache request specifies a partition identifier indicative of an execution environment associated with the cache request. The victim cache entry is selected based on re-reference interval prediction (RRIP) values for a candidate set of cache entries. The RRIP value for a given cache entry is indicative of a relative priority with which the given cache entry is to be selected as the victim cache entry. Configurable replacement policy configuration data is selected based on the partition identifier, and the RRIP value of the new cache entry is set to an initial value selected based on the selected configurable replacement policy configuration data.

    Arbitrating circuitry and method
    9.
    发明授权
    Arbitrating circuitry and method 有权

    公开(公告)号：US10592439B2

    公开(公告)日：2020-03-17

    申请号：US16386321

    申请日：2019-04-17

    申请人： ARM Limited

    发明人： Andrew David Tune ,  Peter Andrew Riocreux ,  Alessandro Grande

    IPC分类号： G06F13/14

    摘要： Arbitrating circuitry arbitrates between a plurality of inputs and a selection of at least one of said plurality of inputs. The arbitrating circuitry includes an array of interconnected arbiter devices operating with respect to a set of Q inputs. The array comprises M sub-levels with at least a first sub-level having T arbiter devices each operating with respect to U inputs, where Q=UM and Q=TU. For each sub-level other than a first sub-level, each arbiter device in a sub-level receives as input requests signals indicating an arbitration outcome for two or more arbiter devices in a preceding sub-level and arbitrates between those input requests.

    Cache coherency
    10.
    发明授权
    Cache coherency 有权

    公开(公告)号：US10169236B2

    公开(公告)日：2019-01-01

    申请号：US15133341

    申请日：2016-04-20

    申请人： ARM LIMITED

    发明人： Sean James Salisbury ,  Andrew David Tune

    IPC分类号： G06F12/08 ,  G06F12/0817 ,  G06F12/0813

    摘要： A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure, which of the cache memories are caching those memory addresses; and control circuitry configured to detect a directory entry relating to a memory address to be accessed so as to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories or a coherent agent in instances when the directory entry indicates that another of the cache memories is caching that memory address; the control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control.